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Thread: Yup, another IBM 5160 failed motherboard

  1. #31
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    Quote Originally Posted by tonata View Post
    When the POST configures a pin in 8255 as an output then what voltage is expected?
    During the 5160's POST, the POST changes the output state of the PB7 pin a few times. The final state is LOW.

  2. #32

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    I got the logic analyzer and I am still learning how to use it:

    I got this so far:

    Logic1.png

    Ch0 -> S0 0n 8088
    Ch2 -> S1 0n 8088
    Ch4 -> S2 0n 8088

    Ch6 -> BIOS pin 20 CE
    ch1 -> READY pin on 8088

    I am trying to understand if it is OK.

    Below is the documentation for 8088:

    STATUS: is active during clock high of T4, T1, and T2, and is returned to the
    passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is
    used by the 8288 bus controller to generate all memory and I/O access control
    signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning
    of a bus cycle, and the return to the passive state in T3 and Tw is used to
    indicate the end of a bus cycle.
    These signals float to 3-state OFF during ‘‘hold acknowledge’’. During the first
    clock cycle after RESET becomes active, these signals are active HIGH. After
    this first clock, they float to 3-state OFF.

    S2 S1 S0 Characteristics:

    0(LOW) 0 0 Interrupt Acknowledge
    0 0 1 Read I/O Port
    0 1 0 Write I/O Port
    0 1 1 Halt
    1(HIGH) 0 0 Code Access
    1 0 1 Read Memory
    1 1 0 Write Memory
    1 1 1 Passive

  3. #33
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    You have a second IBM 5160 motherboard, a good one. You can do a comparison.

  4. #34
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    I decided to take a break from my to-do-list.
    I pulled out my logic state analyser.
    The partial screen shot at [here] shows what my analyzer sees in the 10 μs after RESET is de-asserted on my IBM 5160 motherboard.
    Can be seen are:

    - The 8080/8288 state alternating between 'Passive' (7) and 'Read Memory' (4) as ROM U18 is being read.

    - ROM U18's /CE bin being asserted at some time in the 8080/8288 state of 'Read Memory'.

    - Bytes exiting ROM U18:
    - The EA/5B/E0/00/F0 are the 5 bytes starting at address FFFF0, and together, are a jump to FE05B (F000:E05B) which is the starting address of the POST in my 5160.
    - FA/B4/D5 are the first three bytes of the POST, being the code starting at FE05B.

    You have an analyser of only 2 MHz maximum sampling rate. I changed the sampling rate on my analyser from 100 MHz (0.01 us) down to 2 MHz (0.5 us), and the capture then presented is shown at [here].
    Not enough resolution to see the state pins changing as frequently as they do, but enough to see alternation between 'Passive' (7) and 'Read Memory' (4).
    Enough resolution to see the data out of the U18 ROM.

  5. #35

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    Thanks a lot I will look into it tomorrow (getting late here).

    I do not know how to set my logic analyzer to show codes like yours: EA, 5B ... I am searching for this. What interpreter did you select in your logic analyzer?

    I just want to sum up where the problem can be in general if I do not see the POST:

    - the address bus workflow: CPU -> U6/U7 -> U16/U17 -> ROM might not be working
    - the data bus workflow: ROM -> U15 -> U2 -> CPU might not be working

    The cause is an IC one of the above or not that is probably preventing the address bus or the data bus from working correctly.

  6. #36
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    Quote Originally Posted by tonata View Post
    What interpreter did you select in your logic analyzer?
    None.

    Quote Originally Posted by tonata View Post
    I do not know how to set my logic analyzer to show codes like yours: EA, 5B ... I am searching for this.
    The software that comes with my unit allows me to 'group' pins that I choose, and show a line that displays the hex value of the grouped pins.

    For example, in the screen shot that I provided, I monitored the 8 data pins of U18 (which is the external data bus). I then created an empty group, named it 'U18 ROM data', assigned the monitored eight data pins to the group, then added the 'U18 ROM data' group line to my display.

    The minus sign to the left of 'U18 ROM data' means that I have the option of collapsing the group (i.e. show the 'U18 ROM data' group line, and hide the 'Data0' to 'Data7' lines).

    Quote Originally Posted by tonata View Post
    I just want to sum up where the problem can be in general if I do not see the POST:

    - the address bus workflow: CPU -> U6/U7 -> U16/U17 -> ROM might not be working
    - the data bus workflow: ROM -> U15 -> U2 -> CPU might not be working

    The cause is an IC one of the above or not that is probably preventing the address bus or the data bus from working correctly.
    "Possibly", not probably. There are lots of possibilities. For example, maybe, operation of the address and data buses is good, the POST is starting, but at some very early point in the POST, something goes wrong.

    You have done the basics (except for running the Supersoft/Landmark diagnostic ROM, which you do not have), and you are now going 'deeper' into diagnosis. The deeper you go, the more you need to know about how everything works. For example, what is a 74LS245 bus transceiver chip, the function of each of its pins, and how those pins relate to each other.

    Diagrams such as the 'address bus' and 'data bus' ones at [here] are very simplified. They do not show supporting chips, chips that may be at fault. For example, referring to chip U15 in the diagram at [here], not shown are the chips on the motherboard that are involved in instructing chip U15 as to which direction to use. For example, what instructs chip U2 as to when the multiplexed address/data bus contains data?

    Following de-assertion of RESET, see what is coming out of the IBM BIOS ROM U18. The diagnosis direction you then take will depend on what you see. For example, if the first byte is not EA, you then have to work out why. If it is EA, are the following bytes being read as expected.

    You have a good 5160 motherboard, and so can use that to verify that you are using your logic analyser properly.

  7. #37

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    My logic analyzer is capable of 24MS/s which for 4.73 Mhz signal seems OK. 4.73 x 5 (min of 5 points) = 23.65 < 24 MS/s.

    Thanks a lot! Your photo and the arrows showing the bytes helped me a lot to understand it. Thanks!!!

    OK, so we are reading the status pins in this direction: S2 S1 S0. So after the -5ms we have Hi, Low , Low which corresponds to 1 0 0 = read memory.
    Then at -4.3 we see the CE pin going Hi in response to the memory read request. There is some delay between the Read Memory (4) and the CE response.
    And you are checking the pins Q0 to Q7 which are 11, 12, 13, 15, 16, 17, 18, 19 and it should be read from the direction 19 to 11 (without 14 ground).
    Last edited by tonata; December 7th, 2020 at 01:08 AM.

  8. #38
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    Quote Originally Posted by tonata View Post
    My logic analyzer is capable of 24MS/s which for 4.73 Mhz signal seems OK. 4.73 x 5 (min of 5 points) = 23.65 < 24 MS/s.
    I have put a '20 Mhz sampling' version of my capture at [here].

    Quote Originally Posted by tonata View Post
    Thanks a lot! Your photo and the arrows showing the bytes helped me a lot to understand it. Thanks!!!
    I expect that this thread will be educational to others as well.
    For that reason, you may have seen me write things that I know, from our earlier offline discussions, you already know.

    Quote Originally Posted by tonata View Post
    OK, so we are reading the status pins in this direction: S2 S1 S0. So after the -5ms we have Hi, Low , Low which corresponds to 1 0 0 = read memory.
    Then at -4.3 we see the CE pin going Hi in response to the memory read request. There is some delay between the Read Memory (4) and the CE response.
    For the U18 ROM, the PCB connects the /CS and /OE pins together. Because they are connected, there is no point in displaying both. I simply chose to monitor the /CS pin.

    Both the /CS and /OE pins on U18 are 'active low'. That is why I use a "/" in front of the "CS" and "OE". The pins are normally HIGH. So, in the capture screen shot, you are looking for the /CS pin going LOW (i.e. /CS pin being asserted) (and we know that will take the /OE pin LOW as well). That will result in U18 outputting the data that it has at the presented address.

    The delay between the start of the 'Read memory' state and the U18 /CS pin being taken LOW will be due to delays in the 8288 and delays in the address decode logic.

    And you can see the delay between when U18's /CS (and /OE) pin is taken LOW and when U18 outputs its data. Roughly about 150 ns.

    Quote Originally Posted by tonata View Post
    And you are checking the pins Q0 to Q7 which are 11, 12, 13, 15, 16, 17, 18, 19 and it should be read from the direction 19 to 11 ...
    When deciding what names to give to those signals, I could have chosen 'Q0', 'Q1', 'Q2', etc., but instead, I decided on 'ROM Data 0', 'ROM Data 1', ROM Data 2', etc. At one point, because the ROM's data pins are connected to the external data bus, I thought of naming the signals as 'XD0', 'XD1', etc.

    In order for the software to show hex values (or binary, decimal, etc.), the software needs to know which wires correspond to which bits.

    Quote Originally Posted by tonata View Post
    ... (without 14 ground).
    My 34-channel logic state analyser has 40 wires on its sampling connector. 6 of those are ground wires. If I am measuring, say, only 4 pins, then I will normally use only one of those 6 ground wires, connecting it to a ground on the board, preferably close to the pins that I am measuring. If those 4 pins are all on the one chip, then I would normally have the ground wire connected to the ground pin on the chip.

    If I an doing something like [here], I will normally connect all 6 ground wires.

  9. #39

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    So it seems that your logic analyzer is capable of reading U18 without a clock. Because on the forum of my logic analyzer they insist that a clock signal is required.

    So I will simply use /CE as a clock signal.

  10. #40
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    Quote Originally Posted by tonata View Post
    So it seems that your logic analyzer is capable of reading U18 without a clock. Because on the forum of my logic analyzer they insist that a clock signal is required.
    Yes, my analyser has an internal sampling clock. The default operating mode, Timing Mode, of my software uses it. There is a drop-down in the software that allows me to change that clock (the sampling rate).

    If I wish to use an external sampling clock, I would change the analyser mode from Timing Mode into State Mode, inform the software of which wire ('CLK1' or 'CLK2') I am going to use as the external clock source, then define the clock to data relationship. In recent years, I have not found a need to use an external sampling clock.

    Info: In Timing mode, the CLK1 and CLK2 wires are not special; they are just 2 of the 34 channels available for use.

    Earlier, you pointed to an AZDelivery Logic Analyser. Having a look on the Internet, is very very similar to other 24 MHz units. From what I read, they are clones of the Saleae 8 channel 24 MHz analyser. When I look at videos of the clones, I do not see the an external sampling clock being used.

    At least one of the clones has a 'CLK' pin on its connector where there is a 'GND' pin of others. At first, I thought that was like my analyser, for an optional external sampling clock, but the final post at at [here], reveals that the subject CLK pin is a clock output.

    Your unit must have an internal sampling clock, because your unit showed activity at post #32.

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