The SL82C365 appears to be a 386/486 cache controller
The SL82C365 supports direct-mapped cache system with data size ranged from 16KB to 1MB and line size ranged from 1 to 4 doublewords.
Without any external logic, SL82C365 supports 1 to 4 banks of cache SRAMs independent of the line size. An 8-bit tag comparator is
integrated into the chip which not only saves on the system cost but also improves the overall performance. 25ns tag SRAM and 35ns data
SRAM are adequate for zero wait state non-pipelined 33Mhz operation. Assuming 8Kx8, 16Kx4, 32Kx8 and 64Kx4 SRAMs are used for
tag SRAM, the selectable organization is indicated in Table 1-1. [see datasheet] More options are available for data RAM configurations
because of the flexibility in selecting the number of banks. Refer to section 1.13 [see datasheet] for detailed design examples.
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