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Motorola 6800 interfacing question (a bit OT)

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WimWalther

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Trying to learn the basics of microprocessors, my goal is to control a TI SN76489 music chip with the 6800 (well, 6808 ) cpu on my Heathkit ET-3400A. (For the unaware, the 3400 is a "microprocessor trainer", essentially a single-board computer).

Anyone care to help educate me?
I'm stuck on how to handle the three control lines on the chip: CE, WE & READY.

My current ideas are to connect CE to line A15 and READY to MR on the cpu. I don't know where to go with WE.
 
My 'take' would be to follow the example of the ET-3400A schematic prelatic to how the RAM is wired up.

I would wire the WE pin (which is actually /WE) to the R/W pin of the 6800 cpu (or - more correctly - the buffered version of it after the CPU pin (i.e. the same location as the R/W pins of the RAM).

I would then wire the /CE pin of the sound chip to one of the decodes already available from IC2, IC3, IC20 or IC21 (these are SN74LS42 BCD to binary decoders). This will place your sound generator somewhere in the 6800's memory map - you just have to work out where by decoding the address line logic involved. This logic already includes the /VMA and PHI2 signals that you will also need.

I would ignore the READY output for now. The sound generator may be fast enough that you may not need to hold the 6800 microprocessor up. If you do, wire it to MR as you have stated. EDIT: However, I can't find MR on IC11... Is this a 6800 or 6802?

If this is confusing - let me know and I will take it more slowly.

Incidentally, the data sheet I downloaded for the sound device definitely contains some inconsistencies (/WE and /OE pins for one). I used this: http://www.vgmpf.com/Wiki/images/7/78/SN76489AN_-_Manual.pdf.

The ET3400 manual I used was found at: http://tubularelectronics.com/Heath...als_E-F/ET-3400/Heathkit_3400_595-2021-06.pdf.

Dave
 
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It's a 6800 but with a 6875 clock generator.

The MEMORY READY is implemented through pin 6 of the 6875 - which appears to be physically tied to +5V (i.e. the memory is always ready).

Ah, but you say you have a 6808 - so I must be using an incorrect schematic... Let me check. Ah, I have the ET3400 schematics and not the 'A'. Let me have another look...

Found a better schematic of the right thing this time at http://www.robotsandcomputers.com/computers/manuals/et3400/et3400a_schematic.jpg.

As you were - READY to the MR pin!

I think everything else is the same as I have already posted with regard to /CE and /WE.

Dave
 
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There is a lot of good data at http://www.robotsandcomputers.com/computers/misc_et3400a.htm (but - I guess - you already have the paperwork with your ET3400A anyhow?)

I would wire your /CE to U2 pin 2.

This would decode your SN76489 at 0010 000x xxxx xxxx or $2000.

Code: 
LDX #$2000 ; Point the index register at the SN76489.
LDA A,#$nn ; Load the value to output to the SN76489 into accumulator A.
STA 0,X ; Output the value in accumulator A to the SN76489.

Obviously, this is a bit of crude code...

If you don't want to start soldering wires onto U2, then you will have to decode the addresses and VMA/PHI2 yourself with your own logic following a similar structure as the Heathkit for U2.

Dave
 
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Dave,

Thanks, this is fantastic to have your assistance. FYI that bitsavers link isn't answering, like the server is down.

What is wrong with my idea of CE to A15? Won't that give me an enable signal when I address any location $8000 or above? Pretty sure that all the address space above ca. $2000 is wide open.
 
Isn't the ROM and the 7-segment displays above $8000? Ok, these are read-only, but is R/W used in the decode I wonder?

The other thing missing is /VMA (valid memory address) and PHI2 (the second clock phase). Both of these should be used to qualify the address bus. Look up these signals in the 6800 datasheet.

The manual on bitsavers is a VERY big download - so may take a while...

Dave
 
WimWalther said:
Dave,

Thanks, this is fantastic to have your assistance. FYI that bitsavers link isn't answering, like the server is down.

What is wrong with my idea of CE to A15? Won't that give me an enable signal when I address any location $8000 or above? Pretty sure that all the address space above ca. $2000 is wide open.
Click to expand...

Also, it is not CE it is /CE. This means it is selected if it is zero, not one. You will usually see this as /CE, CE* or CE/. All of these mean inverted. Besides, you need to include /VMA and PH2. If you haven't looked at a data sheet you should look at the 6800's sheet. It will show you a timing diagram of a memory write or a memory read. It will show you a lot of timing requirements for many of the signals from the processor. You need to look at that diagram until you fully understand what setup and hold time mean. I find it confusing to go back and forth to the timing table and the diagram so I usually make a larger copy of the timing diagram and write the numbers with min or max with them.
It is not hard but it is what is required by the processor to keep the data bus in control.
Dwight
 
Dwight Elvey said:
Also, it is not CE it is /CE. This means it is selected if it is zero, not one. You will usually see this as /CE, CE* or CE/. All of these mean inverted.
Click to expand...

Chuck,

Thanks. I do understand the concept (and notation) of 'active low'. I was just being sloppy, and presumed everyone would know that 'CE' was Chip Enable, with or without the /slash.

I find the timing diagrams for the 76489 confusing, one thing being that they use undefined symbols that I'm not familiar with like 'Tpll'. What's that, Time of the Phase-Locked Loop? No. And I don't see it explained.
 
I would guess that T[sub]pll[/b] refers to the time that the phase-locked loop frequency generator acquires a lock from being changed.

But that's just a guess.
 
Chuck(G) said:
Sorry, that'd be Dwight not me.
Click to expand...

Oops, my bad.

And for the record, acquiring all of the relevant documentation is the first step I take when starting a project or job. So yes, I do have all the required manuals, datasheets and so on.

I should also mention that my ET-3400 also has the ETA-3400 expansion module. The latter adds 4K RAM, a BASIC / monitor ROM and a Peripheral Interface Adapter chip that seems to be a form of UART, as it handles serial communications.
 
If you have the ETA-3400 as well then you need to understand what the complete memory map is for the entire machine. You have to then work out the most suitable location to put your sound chip to cause no interaction with anything else.

My recommendation was based upon a bog standard ET-3400...

Dave
 
The sum of all RAM & ROM in the machine is not much more than 8K I believe (4K RAM + 2x 2K ROMs plus the small OS ROM).

I'll look it over again to be sure, and post any corrections at that time.
 
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It is not necessarily the sum total of the Ram and ROM you need to look at.

The seven segment displays and the keyboard also occupy memory space (the MC6800 CPU has memory mapped peripherals).

Also, some of the address space can be 'mirrored' (due to incomplete address decoding) making it unusable as well.

The user manual should identify the memory map of the machine.

On page 87 of http://www.robotsandcomputers.com/computers/manuals/et3400/et3400_trainer.pdf it identifies the memory map for the standard ET-3400. I note three (3) "not usable" spaces (possibly to do with the keyboard and display decoding). The RAM is at the bottom and the ROM/keyboard and display at the top of memory - hence using A15 as the /CE won't work on its own - as the TI sound device will be enabled at the same time as RAM access. Conversely, if you invert the signal, the TI sound device will be enabled when the ROM keyboard and/or display is updated. Neither of these scenarios is desirable :). Further address decoding is therefore required.

Dave
 
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As a general rule, with 6800 (and 6502) systems, there is RAM at the bottom and ROM at the top of the memory map.

Processor vectors lie at the very top of $FF page, and $00 page is essentially a bank of slow registers, due to the Direct addressing mode.
 
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