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Commodore 8032 add-on board - SuperPET

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    Commodore 8032 add-on board - SuperPET

    This is a bit of an 'out there' question but I am looking for an 'interesting' hardware project over the winter. Thoughts strayed to an add-on board for a bog standard 8032 to turn it into a SuperPET. Would there be any interest and (if so) what am I aiming for as a requirements specification?

    Starter for 10:

    Modern 64K (2*32K) static RAM instead of DRAM.
    6809 firmware held in 1*27256 EPROM.
    No ACIA port.
    No 6702 'dongle' - I presume to use my 'de-dongled' Waterloo software.
    Incorporation of the TPUG MMU to be able to run OS/9.
    Convert a lot of TTL glue logic into PALs.

    Anything else?


    Originally posted by daver2 View Post
    Anything else?
    Count me in. Some other requirements to think about:

    * Make sure standoffs for new board are long enough not to interfere with RAM/ROM Replacements boards.

    * Mount switches on new board to simplify cabling.

    * Use solid state relay or equivalent to switch off 6502 (in 6809 mode) rather than using a regulator and 2 transistors.

    * Without the need for the memory refresh circuitry due to using static RAM, perhaps clock/counter circuits can be simplified.

    * Incorporate a test connector header for use with logic analyzer for ease of troubleshooting.

    * Incorporate a NOP Generator and perhaps a diagnostic ROM that can be switched in to initialize CRTC, run RAM tests and ROM sum checks, etc.

    * Use high grade machined pin sockets and leave room between sockets to use DIP Clips and other troubleshooting aids.


      Yes, that would be cool. Something ive been thinking of for quite a while.

      WANTED: CBM-II hardware or software, PET software


        Great idea.
        Not "out there" at all!


          Originally posted by daver2 View Post
          Convert a lot of TTL glue logic into PALs.
          If it turns out we use the PAL22V10 or similar, I can supply programmed parts (gratis) to users without a burner. I can also burn GALs but do not have an assembler program to create the proper JEDEC file for those types from design equations.

          However, if we can fit all the parts into a small enough board without PLDs, I think most users would prefer not to have 'semi-custom' parts. Remember the crazy Signetics 82S100 part used in the C64. Of course if we do use PALs, we would not burn the security fuse and we would distribute the design files.



            I'm wondering if it's possible to design the board so it's compatible with the 8296 motherboards? I've always loved the rounded case of those models. The 8296 comes standard with 128K ram, so that may pose a problem.

            WANTED: CBM-II hardware or software, PET software


              Originally posted by sjgray View Post
              I'm wondering if it's possible to design the board so it's compatible with the 8296 motherboards?
              Hi Steve,
              daver2 is the Chief Systems Engineer (I elected him!) and will decide the final requirements for this board, but for clarification, I have a question.

              Are you asking for the capability to turn an existing 128K Commodore 8296 into a SuperPet with a board that will meet functional and size requirements to fit in the smaller case? One possible issue might be video RAM. Do you know if video RAM is mapped at $8000 in the 8296 as it is in the 8032?
              Last edited by dave_m; August 28, 2015, 06:27 PM.


                Originally posted by dave_m View Post
                Hi Steve,
                daver2 is the Chief Systems Engineer (I elected him!) and will decide the final requirements for this board, but for clarification, I have a question.

                Are you asking for the capability to turn an existing 128K Commodore 8296 into a SuperPet with a board that will meet functional and size requirements to fit in the smaller case? One possible issue might be video RAM. Do you know if video RAM is mapped at $8000 in the 8296 as it is in the 8032?
                I second the nomination!
                Yes exactly.
                Yes, video ram is at the same location. In fact, you can allocate up to 8k ram for video on the 8296 by jumpering the expansion space (normally for roms) at $9000 and $A000 to instead be RAM.

                The 8296 board is almost the same layout as the 8000 series motherboards but less deep. If possible it would be nice if the board also fit inside an 8296D machine with the built-in disk drives. Ok, you got me...


                WANTED: CBM-II hardware or software, PET software


                  I don't know much at all about the SuperPET, but why would you eliminate an ACIA?
                  Be polite and I may let you live.



                    Originally posted by KC9UDX View Post
                    I don't know much at all about the SuperPET, but why would you eliminate an ACIA?
                    The University of Waterloo in Ontario designed the SuperPet to be a smart remote terminal for their mainframe. Software development would be done on the SuperPet, but data storage would be on the mainframe. The serial link supported this requirement. However in the age of PET SD drives, this link may not be as useful. The thinking is, the more requirements that can be trimmed, the smaller the board. Of course using more modern parts will help the most. A 32K static RAM will replace eight dynamic RAMs and several counters and multiplexers required for the refresh logic.


                      Including the ACIA would be nice if there is room. I believe the SuperPET board has 64K ram, not 32K. I have seen 64K skinny-dip srams on ebay.

                      Looking at schematic 9000016:

                      * U22-U28 DRAM - Replace with one 64Kbyte SRAM - savings 7 chips
                      * U45-U49 ROM - Replace with one EPROM - saving 4 chips (or empty socket space)
                      * U41 - 6702 protection chip - remove - saving 1 chip
                      * U40 - 6551 ACIA serial chip - remove? - saving 1 chip
                      * U38/U39 - RS-232 support chips - remove? - saving 2 chips
                      * U8-U11 - mux chips for adressing DRAM - not needed - saving 4 chips
                      * A few additional chips used for address decoding can also be eliminated (U33/44/45 and probably more).

                      So that's at least 19 chips. Probably closer to 25 out of about 45 total chips.

                      Can anyone see any more that can be removed/reduced?

                      Last edited by sjgray; August 29, 2015, 06:10 AM.
                      WANTED: CBM-II hardware or software, PET software


                        Originally posted by sjgray View Post
                        Can anyone see any more that can be removed/reduced?
                        Counters U3 and U4 are only used to create sequential addresses for RAM refresh. Mux U7 and flip flop U14 seem to be selecting clocks for the CAS and RAS refresh signals. Using transistors Q1 and Q2 along with voltage Regulator VR1 seems an inefficient way for switching power off to the 6502.


                          Thanks for the vote of confidence .

                          Sorry to be quiet for a few days - I was finishing off my vacation in New York and was flying back to the UK on Thursday evening. I am now just recovering from the jet lag!

                          To sum up:

                          It seems to be a good idea to provide an add-on 6809 board for the Commodore PET to turn it into a SuperPET.

                          Yep - the ACIA wasn't extensively used by the community (only as a link to a 'host' mainframe computer) but I am sure there are a couple of programs out there that use it (but I don't think it a valuable add-on for this exercise).

                          I am preferring to use 2 off 32K*8 SRAM chips to one 64K*8 chip. This makes the PCB slightly more complex - but the 32K*8 device is widely available and cheap and could be substituted if the supplier I used decided not to produce them anymore.

                          I am looking at the following:

                          1 off 40pin DIL header (for connection in place of the PET's 6502 CPU).

                          1 off Western Design Centre W65C02S6TPG-14 as the 6502 CPU (this supports a BE pin to disable the address/data and R/notW line in a similar manner to the 6809E's TSC, uses a single PHI2 clock and is readily available at a reasonable price from a UK/USA stockist).

                          1 off S6809EP CPU (stocks of this exist within a major UK distributor from AMI (American Microsystems Inc - now ONSEMI) so I am reasonably confident that these devices are not fakes or counterfeits and are a reasonable price).

                          2 off 32K*8 CMOS SRAMS.

                          1 off 27C256 32K*8 EPROM (or an equivalent EEPROM).

                          I will try and design the circuit to accommodate different manufacturers devices for the SRAM and (E)EPROM to keep our options open for future obsolescence.

                          I will have to generate a clock for the S6809EP (Q and E pins). I don't particularly like the circuits used in either the 1 or 2 board SuperPET as they seem to contain design errors. I am, therefore, planning to use the clock generator circuit from the 6809E data sheet (a 74LS76 and 1/6 74LS04 with an additional pull-up resistor). Unfortunately, this means that I will need a 4 MHz 'flying-lead' from the PET master timing circuit. Let me think about this one a bit more...

                          The 74LS123 (U12) will remain for the CPU changeover reset logic.

                          I can't justify the 'NOP generator' to myself (I only have the hobbyist copy of Eagle so 160x100 mm is the maximum size of the PCB I can design - and I tend to space out my components quite a lot rather than cram then in). Can you persuade me Dave?

                          Quite happy to entertain the on-board switches to select 6502/6809/PROG and RO/RW/PROG - but can you give me a little more detail why you think they would be useful? I would have thought most people would want a 6502/6809 switchable solution and the RO switch option is not much use hard-wired on its own.

                          I agree with the 'non-PAL' solution - but I may run into PCB design constraints if I don't use a PAL (due to the large number of 'glue' devices) if I am not careful. I have an 'aged' GAL 16x8 and 22x10 programmer which I would like to upgrade anyhow. I can't see these devices becoming obsolete for a fair while. I notice Lattice have stopped doing them - but ATMEL have picked up the range and extended it I see. I suspect my programmer won't program ATMEL devices though... I have the software to produce the JEDEC file from the logic equations though.

                          Incidentally, using the W65C02 means that I potentially don't need the horrid switchable 5V supply (I can keep the 6502 CPU powered all the time) and, therefore, that I don't need the +9V unregulated supply (just the regulated +5V supply is all I need if I ignore the serial converters - another reason for not incorporating the ACIA).

                          The use of low-power parts (as far as practicable (e.g. CMOS SRAM and (E)PROM) and the much reduced 'glue' logic should mean that I can use the regulated +5V supply from the PET 6502 CPU pins...

                          Unless anyone has any concerns with what I have written above, I will wire-wrap up my prototype design (bringing the 'control' signals out to a header for now) and then start to think about the PAL logic in parallel.

                          I also plan to add a RESET switch to the PCB if anyone wants to fit it.

                          I will ignore U45 and U46 (as these were used as additional ROM sockets for the 6502 if my memory serves me correctly), and 'compress' the software that occupied U47, U48 and U49 into my single EPROM (mapped from $A000 to $FFFF in the 6809 address space). I will still need a modified character generator for the PET to access the additional characters that the SuperPET required (e.g. the APL character set).

                          There are a couple of issues that I am confused by at the moment:

                          1. Under what circumstance is the DIAG bit (U35/3) of any use? I know it causes the 6502 PET to enter the debug monitor when activated - but I can't think of any use in 6809 mode.

                          2. I/O port $EFFE data bit 0 seems to swap RAM for ROM. Do I need to implement this for the 6809? I don't think so and, therefore, U37 can be omitted.

                          3. U37 data bit 7 (memory map register) seems to be used to enable/disable the clock for U35 on the combined SuperPET board. It doesn't seem to be wired on the 2-board set. If this is the case, then the software should not use this bit and I can omit it.

                          It's midnight in the UK so I think I had better go to bed before I fall to sleep at the keyboard!!!




                            I also forgot to say that this board should work for any PET that supports the same 'hardware' features of the 8032. The limitation is not what I am doing (necessarily) but that the Pet hardware is compliant with the 6809's firmware and Waterloo languages. If that holds - you should be 'good to go'.

                            There are two (2) 'sneaky' tricks that I can see that Commodore did to support the SuperPET (using the universal 8032 at any rate). One was to sneak a 16 MHz clock into an N.C. pin (35) on the 6502 socket. This was via a link on the universal PET. The other is to wire the /NOROM signal up to another N.C. pin (5). My plan is to retain the /NOROM trick - but have a separate fly-lead for the 4 MHz clock. I 'may' (on reflection) keep the 16 MHz input from the 6502 PET socket and divide it by 4 (using a 74LS74) to give me my 4 MHz for the 6809 clock generator.

                            Any thoughts?

                            This would keep the clock fairly 'simple' but would require a PET main board that had this clock as standard (or a PET modification). I could make this link selectable and use either pin 35 as the clock or an external flying-lead from a header depending on the link setting. Thoughts?



                              I see lots of UM61512AK 64Kx8 sram chips on ebay for less than $3 each in bulk. I don't think they'll disappear any time soon. I don't know if they are suitable timing/access-wise but using them would definitely save board space.
                              Every PET already comes with a 6502, so not sure you should probably just use it rather than use a different version unless the gain from tri-stating the bus makes it cheaper in the long run.
                              The SuperPET also had a 4K character ROM chip which contained ASCII/APL characters.

                              I'm excited to see this happen!

                              WANTED: CBM-II hardware or software, PET software