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Commodore 8032 add-on board - SuperPET

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    #31
    Hi Mike - welcome to the thread.

    Thanks for the responses (everyone).

    I didn't realise the serial port was available for use as a 'virtual file system' - so I am convinced that we need the ACIA and buffers now! (It is always good to talk!)

    Current Specification:

    6502 @ 1 MHz (modern part - no silly switchable voltage regulator).
    6809 @ 1 MHz (difficult to see how to support anything faster given that we will be 'overdriving' the PET 8032 main board PHI2 signal).
    Single SRAM device (512K * 8, 32 pin, 0.6" device package). The reason for the larger RAM 'footprint' will be divulged shortly...
    Single 27C256 OTP EPROM (containing the Waterloo firmware).
    TPUG MMU (to support OS9).
    ACIA + RS232 buffers + DB9 connector.
    Single +5V operation (as low power as can be achieved - to be advised).
    Reset switch (optional).

    I have now settled on a 4 MHz external TTL clock signal (following the Motorola data sheet circuit) to derive the 6809s E and Q quadrature clocks). This will be link selectable to be sourced via either the 6502 socket or a separate 'flying lead'.

    Separate character generator to replace the device in the 8032 PET main board (probably a 2532 EPROM - or larger device - with an adapter).

    There will be no support for:

    NOP generator.
    Onboard switches (all external connections will be via a multi-pin 0.1" header [in addition to the 6502 socket of course] to enable easy board installation and removal).
    6702 protection device (Waterloo languages now de-dongled and unlikely this device will have been included with other software).
    Onboard 6502 ROM devices.

    How would that satisfy everyone?

    Dave

    Comment


      #32
      That sounds good!
      WANTED: CBM-II hardware or software, PET software

      Comment


        #33
        Agreed!

        Comment


          #34
          Cool enough for me!

          6809 @ 1 MHz (difficult to see how to support anything faster given that we will be 'overdriving' the PET 8032 main board PHI2 signal).
          Well, maybe the 6309 replacement would be enough, if it works and there're no synch (are both processors synched in some way?) issues, it gives a 20% boost out of the box

          Comment


            #35
            Originally posted by jltursan View Post
            Cool enough for me!



            Well, maybe the 6309 replacement would be enough, if it works and there're no synch (are both processors synched in some way?) issues, it gives a 20% boost out of the box
            The 6309 will work in the current superpet. When the 6809/6309 are active the 6502 is powered down. There is no sync. Any time you switch from one to another the processor reboots.

            Steve
            WANTED: CBM-II hardware or software, PET software

            Comment


              #36
              I have also checked out the data sheets - and come to the same conclusion that Steve has that the 6309E is pin-compatible with the 6809E (note the significance of the 'E' - for external oscillator). Looking around for sources of the 6309E - I find them a bit scarce (even on e-bay) - if you discount the 10,000 new parts per month I can purchase from China...

              I will stick with the 6809E for now - but I see no reason why just plugging a 6309E into the socket would not work at this point in time.

              I have just downloaded and installed KiCAD onto my iMac under OS X - so I now have a bit of a learning curve to go up to get the PCB done. Unfortunately, work calls and I have to be away this week (still, I can watch the KiCAD tutorials and make my notes whilst sitting in the hotels).

              Dave

              Comment


                #37
                Dave,
                Any update on the SuperPet board project? I know that real life can get in the way of fun projects.
                -Dave

                Comment


                  #38
                  Dave,

                  Unfortunately, real 'work' has taken over my life at the moment (and has done since I got back from holidays last year). I managed to sketch out whilst on holiday exactly what I wanted to do and have managed to get about half of it into KiCAD (schematic capture) at the moment.

                  I will spend a bit of time this week and next trying to get the bulk of the remainder in - leaving the address decoding 'glue' logic until later (I will have to think about that some more).

                  I have the two processors, RAM, ROM and clock logic done so far. I stalled a bit on the ACIA - but know exactly what I want to do. Also need to add the reset logic.

                  I was discussing with someone about porting Nitros9 to the beast - so I have decided to go with the SuperPET MMU scheme and I have found a stock of TI SN74LS610 MMU chips (Think Tandy CoCo) so I will add one of those for the extended memory management.

                  I will release a PDF of the schematics when I have got everything in (apart from the glue logic) for comments.

                  Thanks for the reminder Dave...

                  Dave

                  Comment


                    #39
                    Originally posted by daver2 View Post

                    Unfortunately, real 'work' has taken over my life at the moment...
                    Enough said. We will be patient as we know this is a big project.
                    Best regards,
                    Dave

                    Comment


                      #40
                      Originally posted by dave_m View Post
                      Enough said. We will be patient as we know this is a big project.
                      Best regards,
                      Dave
                      Yep, agreed. Take your time.

                      Comment


                        #41
                        Thanks guys...

                        6551 ACIA and MAX232 level converter schematic complete.

                        Dave

                        Comment


                          #42
                          I have a 'first cut' of the schematics done - but the file is a bit large to upload to the forum. If anyone wants a copy of the schematics in PDF form - PM me and I will send you a copy for comment.

                          There are a few things outstanding at the moment:

                          1. The title blocks on the individual schematics need tidying up.
                          2. There is a DRC error for the PHI2 clock pin of the 65C02 CPU (not sure what to do with it at the moment - I suspect it should be my SYSTEM_E clock).
                          3. There are some DRC errors on unused pins of the EEPLD (Atmel ATF1508AS for the glue logic).
                          4. I may need to put the 65C02 into "not ready" mode (Set the READY pin low) when the 6809 has control. I have some spare pins on the EEPLD for this if necessary.
                          5. I am not 100% convinced about my clock logic yet...
                          6. I am even less convinced about my memory mapping scheme! OK with the 6502/6809 part - but not how it will work with NitrOS-9 Level 2.
                          7. I need to add some more decoupling capacitors and tidy up the schematic accordingly.

                          It is a little late in the UK at the moment - so I am sure when I review the printed schematics tomorrow I will have some comments of my own...

                          I will also describe my memory mapping scheme in detail when I have had a good nights sleep.

                          Dave

                          Comment


                            #43
                            Keep up the good work.

                            I'm thinking of converting my 4032 over for this. I've already got 3 6309's laying around that I bought to upgrade cocos.

                            Later,
                            dabone

                            Comment


                              #44
                              Originally posted by daver2 View Post
                              There are some DRC errors on unused pins of the EEPLD (Atmel ATF1508AS for the glue logic).
                              Dave,
                              Wow, we are going high tech. Will you be using the 84 pin PLCC or the 100 pin PQFP pin package? I hope these won't be too hard to solder. Or is there some kind of handy socket available that will make life easier to solder the board? I guess you will bring out the JTAG ISP pins to a header to allow easy on-board programming using the free Atmel software?

                              This is going to be an amazing project.
                              -Dave

                              Comment


                                #45
                                Dave,

                                The 84 pin PLCC has enough pins to do the job. The plan is to use a socket for the beast - so the pins will be on a 0.1" pitch for the PCB (nice and easy to solder). See http://uk.farnell.com/multicomp/mc-8...ole/dp/2097218 for an example of a socket.

                                I'll be bringing out the JTAG pins to a small header yes.

                                The use of this device has made the 'glue logic' and the PCB much easier. I have kept all the flip-flops and latches external (so the BANK SELECT and SYSTEM latches are still 74LS273s for example). The EEPLD should just contain combinatorial logic. It also means I can make the odd error or two and maybe get away with it by reprogramming the EEPLD!

                                Dave

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