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New project - the ROMulator, successor to the PETvet (RAM/ROM replacement plus debug)

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    New project - the ROMulator, successor to the PETvet (RAM/ROM replacement plus debug)

    Hi all,

    I'd like to introduce a project I've been working on for a couple of months now.
    Tentatively called the ROMulator, it's a RAM/ROM replacement board for the Commodore PET (and potentially other 6502 machines) as well as a debug interface which allows you to halt the 6502 CPU and read and write to/from the memory map. This is a direct replacement/successor to the PETvet, which was an earlier board of mine from a couple of years ago.
    It's implemented with a Lattice ICE40 UltraPlus FPGA, which implements the memory decode/enable logic as well as the full 64k memory map. Currently it supports up to 16 selectable memory maps with a dip switch. Portions of memory can be selected to be replacement RAM (read/write), replacement ROM (read-only), passthrough which bypasses the ROMulator and goes to the mainboard bus, or writethrough which echoes writes to the main bus and to the ROMulator. This is useful for capturing writes to screen memory which can be viewed in the debugger. Memory map properties are currently selectable at a granularity of 2048 bytes, but this can be an arbitrarily small number controlled by software.
    There is sufficient RAM available on the FPGA to not only replace the full memory map for the PET, but also do bank swapping controlled by writes to special addresses. Can enable some interesting software development.

    My goals with this project were to create a capable RAM/ROM replacement in as small a board as possible, at low cost. Also wanted the chance to learn about FPGA development, which was an interesting voyage. The ICE40 FPGA is the most expensive part at about $5, and I estimate the final price of the ROMulator to be in the $25 range.

    I'm getting in the latest rev of the board later this week, and if anyone is interested I will have a few early versions available, just let me know. If there's enough interest I plan to make these in larger volumes.

    IMG_2903.JPG

    Please let me know if you have any questions, thanks!
    - Mike

    #2
    Long time no see/hear, Mike.

    I definitely need one of these to add to my collection of PET tools; put me on the list.

    Coming up for the WoC?

    mike in TO.

    Comment


      #3
      This is a great project potentially useful to a lot of owners of other systems. Hardly anyone makes them commercially anymore and they were expensive last time I looked. I recently made a special purpose 2716/2708 model for building/programming a 4004 instead of burning and learning. I dont know how to do FPGAs so I did it with a PIC and (now rare) dual-port RAM.

      Comment


        #4
        Good to see you around again.

        Project looks really neat. Is the FPGA on that carrier board or is it integrated on the lower circuit board? I assume the $5 price for the FPGA is just the bare die?
        My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

        Comment


          #5
          Good to see you are still doing this stuff Mike. Sounds great.

          Tez
          ------------------------------------------------
          My vintage collection: https://classic-computers.org.nz/collection/
          My vintage activities blog: https://www.classic-computers.org.nz/blog/
          Twitter: @classiccomputNZ ; YouTube Videos: (click here)

          Comment


            #6
            Originally posted by gubbish View Post
            Hi all,

            I'd like to introduce a project I've been working on for a couple of months now.
            Tentatively called the ROMulator, it's a RAM/ROM replacement board for the Commodore PET (and potentially other 6502 machines) as well as a debug interface which allows you to halt the 6502 CPU and read and write to/from the memory map. This is a direct replacement/successor to the PETvet, which was an earlier board of mine from a couple of years ago.
            It's implemented with a Lattice ICE40 UltraPlus FPGA, which implements the memory decode/enable logic as well as the full 64k memory map. Currently it supports up to 16 selectable memory maps with a dip switch. Portions of memory can be selected to be replacement RAM (read/write), replacement ROM (read-only), passthrough which bypasses the ROMulator and goes to the mainboard bus, or writethrough which echoes writes to the main bus and to the ROMulator. This is useful for capturing writes to screen memory which can be viewed in the debugger. Memory map properties are currently selectable at a granularity of 2048 bytes, but this can be an arbitrarily small number controlled by software.
            There is sufficient RAM available on the FPGA to not only replace the full memory map for the PET, but also do bank swapping controlled by writes to special addresses. Can enable some interesting software development.

            My goals with this project were to create a capable RAM/ROM replacement in as small a board as possible, at low cost. Also wanted the chance to learn about FPGA development, which was an interesting voyage. The ICE40 FPGA is the most expensive part at about $5, and I estimate the final price of the ROMulator to be in the $25 range.

            I'm getting in the latest rev of the board later this week, and if anyone is interested I will have a few early versions available, just let me know. If there's enough interest I plan to make these in larger volumes.

            [ATTACH=CONFIG]57553[/ATTACH]

            Please let me know if you have any questions, thanks!
            - Mike
            We should talk about my dual-ported RAM FPGA solution that renders a VGA display straight from RAM by snooping on $8000-$8FFFF via a similarly socketed card. It might be a feature you'd want to add, though I haven't used that particular FPGA, so I don't know its capacity.

            Comment


              #7
              I'm in for one.

              Comment


                #8
                I don't understand. The iCE40up5k is not a 5V nor 5V tolerant part. How are you doing level translation?
                "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

                Comment


                  #9
                  Thanks for the messages, all..
                  Has been quite a while since I've been active in the hobby. Had a son a couple of years ago now, and between that and work, haven't had much time for vintage computer stuff recently. But recently I've dusted off the soldering iron and trying to get back into it.
                  Would like to come to WoC, Mike, probably won't happen this year because of the little guy. But hopefully soon travel will be more of an option.

                  The $5 price is just the ICE40 chip itself. It's on a little carrier board which brings the IO out to pin headers and has SPI flash and a couple of regulators and some resistors/caps.
                  As eeguru mentioned, it is indeed not 5v or tolerant, so the board which has the 6502 CPU socket has a few 74LVC245s for level shifting. These are 5V tolerant, but output 3.3V logic for the ICE40.

                  I'll take some better pictures and post a little demo video soon.
                  I'd be very interested in trying the VGA output - the FPGA does have sufficient dual-port RAM to do it - 15KB I believe. As the design is now I believe there are 4 free IOs on the chip, so not enough for full color VGA but I think mono vga would be possible.

                  Comment


                    #10
                    Originally posted by gubbish View Post
                    writethrough which echoes writes to the main bus and to the ROMulator. This is useful for capturing writes to screen memory which can be viewed in the debugger.
                    gubbish,
                    Put me down for one as all your designs are very interesting. Is the debug port going to be some kind of serial interface?
                    -Dave

                    Comment


                      #11
                      Originally posted by gubbish View Post
                      The $5 price is just the ICE40 chip itself. It's on a little carrier board which brings the IO out to pin headers and has SPI flash and a couple of regulators and some resistors/caps.
                      Is the carrier an off the shelf part? Lattice's breakout board for the chip seems to run about $50...

                      Aha! Is it a Gnarly Grey UPDuino? I'd be curious what your thoughts are generally on that as an FPGA learning platform.
                      My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                      Comment


                        #12
                        It is indeed a UPDuino, the 1.0 version. It's surprisingly inexpensive (about $10 I believe) and was very useful for development. I've seen some grumbling on FPGA forums about the layout of it, and apparently there are some issues with the PLL functionality, but for what I was using it for, it worked great. The documentation for it was pretty sparse and I had to cobble together a few things to fully understand how to program the onboard SPI flash vs programming the fpga directly. The main thing was that the upduino documentation is all for use with the Lattice programming software (ICE studio I believe), but I found it much easier to use the open source toolchain for the ICE40 (yosys/arachne/icestorm). I did end up writing a small programmer application for raspberry pi for programming the SPI flash on the board, and the FPGA reloads from flash upon reset. In general, it is a great board for the price and seems to to the job, but there is a little learning curve to just understand how to get the thing running in the first place. It doesn't have any of the bells and whistles of other dev boards.

                        There are, however, a few IO pins available on the chip that are not brought out to the pin headers on the upduino board, so I did another layout to get those extra pins available. Not totally pin compatible with the upduino but either board works with the ROMulator board, with a different pin layout that is controllable in verilog. Hopefully these extra pins will allow VGA output from video ram!

                        Comment


                          #13
                          Regarding the debug port on the ROMulator,
                          currently the debug works over SPI, using a debug application running on a raspberry pi. The FPGA starts out operating as an SPI master, and reads in its own initialization data as well as the PET memory map on reset. Then it switches to an SPI slave, and waits for a debug command to arrive while the system is running. Once the command is received, the 6502 is halted by toggling the RDY line, and the full memory map is sent to the debug application where you can view or modify memory, and if you make changes, can send back the modified memory map. The same connection is used for reprogramming the ROMulator, so you can replace the library of memory maps stored in flash and/or rebuild the FPGA image from verilog if you want to make functional changes. So you can leave it connected and debug a running system
                          Incidentally, the available PET memory maps are stored sequentially in the SPI flash, and the FPGA reads one of the maps into its RAM on reset, controlled by the dip switch setting.

                          Comment


                            #14
                            Another thing to add is that while currently the debug takes place over SPI as described, due to this being an FPGA the same debug pin connection could be used instead as a UART. So if it's useful a serial port debug function could be added, using a 3.3v usb-serial cable.

                            Comment


                              #15
                              Hi Mike,
                              Being one of the early guys to use your PETVet, Please put my name on the list as well for the ROMulator...hopefully it will help me in troubleshooting my PET8032 ( currently at backbench). Thanks

                              Comment

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