bitfixer
Veteran Member
Hi all,
I'd like to introduce a project I've been working on for a couple of months now.
Tentatively called the ROMulator, it's a RAM/ROM replacement board for the Commodore PET (and potentially other 6502 machines) as well as a debug interface which allows you to halt the 6502 CPU and read and write to/from the memory map. This is a direct replacement/successor to the PETvet, which was an earlier board of mine from a couple of years ago.
It's implemented with a Lattice ICE40 UltraPlus FPGA, which implements the memory decode/enable logic as well as the full 64k memory map. Currently it supports up to 16 selectable memory maps with a dip switch. Portions of memory can be selected to be replacement RAM (read/write), replacement ROM (read-only), passthrough which bypasses the ROMulator and goes to the mainboard bus, or writethrough which echoes writes to the main bus and to the ROMulator. This is useful for capturing writes to screen memory which can be viewed in the debugger. Memory map properties are currently selectable at a granularity of 2048 bytes, but this can be an arbitrarily small number controlled by software.
There is sufficient RAM available on the FPGA to not only replace the full memory map for the PET, but also do bank swapping controlled by writes to special addresses. Can enable some interesting software development.
My goals with this project were to create a capable RAM/ROM replacement in as small a board as possible, at low cost. Also wanted the chance to learn about FPGA development, which was an interesting voyage. The ICE40 FPGA is the most expensive part at about $5, and I estimate the final price of the ROMulator to be in the $25 range.
I'm getting in the latest rev of the board later this week, and if anyone is interested I will have a few early versions available, just let me know. If there's enough interest I plan to make these in larger volumes.
Please let me know if you have any questions, thanks!
- Mike
I'd like to introduce a project I've been working on for a couple of months now.
Tentatively called the ROMulator, it's a RAM/ROM replacement board for the Commodore PET (and potentially other 6502 machines) as well as a debug interface which allows you to halt the 6502 CPU and read and write to/from the memory map. This is a direct replacement/successor to the PETvet, which was an earlier board of mine from a couple of years ago.
It's implemented with a Lattice ICE40 UltraPlus FPGA, which implements the memory decode/enable logic as well as the full 64k memory map. Currently it supports up to 16 selectable memory maps with a dip switch. Portions of memory can be selected to be replacement RAM (read/write), replacement ROM (read-only), passthrough which bypasses the ROMulator and goes to the mainboard bus, or writethrough which echoes writes to the main bus and to the ROMulator. This is useful for capturing writes to screen memory which can be viewed in the debugger. Memory map properties are currently selectable at a granularity of 2048 bytes, but this can be an arbitrarily small number controlled by software.
There is sufficient RAM available on the FPGA to not only replace the full memory map for the PET, but also do bank swapping controlled by writes to special addresses. Can enable some interesting software development.
My goals with this project were to create a capable RAM/ROM replacement in as small a board as possible, at low cost. Also wanted the chance to learn about FPGA development, which was an interesting voyage. The ICE40 FPGA is the most expensive part at about $5, and I estimate the final price of the ROMulator to be in the $25 range.
I'm getting in the latest rev of the board later this week, and if anyone is interested I will have a few early versions available, just let me know. If there's enough interest I plan to make these in larger volumes.
Please let me know if you have any questions, thanks!
- Mike