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  • gertk
    replied
    And another update

    The stray pixels were generated by address bus conflicts between the counter outputs and the latch outputs.
    It seems the 74HC590a releases the output quite slow.

    By means of an extra delay in the GAL (connecting an output to an input) I managed to get the outputs of the counters released a little bit before the latches come onto the bus and I can also delay and squeeze the /WR pulse in between. So effectively a write to the SRAM is reduced to a single OUT instruction, that is after setting up the address in the address latches before.
    The 'hash' is now reduced to small stripes (about 200 ns in length...)

    Leave a comment:


  • gertk
    replied
    This is the result so far, no more stray pixels..

    justlines_ok.jpg

    Leave a comment:


  • gertk
    replied
    GAL as latch problem solved: seems the compiler refuses to generate registered outputs if either the CLK pin (pin 1) is named, or the /OE pin (pin 11) is named, or you assign output enables to the (registered) outputs. And it does it silently..

    Progress so far: if I enable the latch and buffer outputs (and thereby disable the counter outputs) with an additional IO line from the PIO and let the BRDY just handle the /WR pulse for the SRAM it works flawlessy, no more pixel errors. Reading and writing is fine.
    Disadvantage of this scenario is speed, I now have to enable the outputs, then perform read or write and then disable the outputs again.
    The hash stripes just get longer this way but at least they are black during this period.

    The /OE and /CS of the SRAM are now constant at GND level, just the /WR gets pulsed.

    Leave a comment:


  • gertk
    replied
    Yes I found out timing is crucial and datasheets can be very unclear... I now have replaced both the HC573 latches with 16V8 GAL's as 74F574 are hard to get and I didn't want to wait (...) hoping they might be a bit faster and edge triggered but now I can not even get those GAL's to work properly... Pfff.... They should latch on the rising edge of the clock signal but al I seem to get is 'transparancy'. Need to fiddle a bit more with those.

    Also the datasheets of the SRAM chips I have are unclear on what signal the data is stored into the cell, only in the IS61C256 datasheet is an example of using the SRAM with /CE and /OE permanently low and it says the write cycle is then /WE controlled. And then I found out that my GAL16V8's programmed as latches didn't work

    Leave a comment:


  • Eudimorphodon
    replied
    For laughs here's a picture of one of those magic "flickering yet persistent" dots on my prototype. Cleaning up the wiring on the breadboard nixed most of them, but that one dot visible under the pterosaur's chin in low-res mode below:

    324proto_32column.jpg

    Was still around, at least in the initial round of testing I did yesterday evening. (I generated a couple new test plates with information useful for actually verifying that I was getting the correct number of pixels per line, et al, and demo displaying different-width framebuffers offset in different memory locations and doing horizontal/vertical hardware scrolling.) I could make it go away by putting my finger on the flash chip, and then disappeared mystly after I yanked out the MCU for reprogramming the second time and shoved some wiring around a little. Curiously the dot was *not* there in high-res mode, even though that's referencing the same location on the same frame buffer, only in low res. Some very minor timing difference...

    (I have a suspicion based on the location of the glitch that this is related to address line A12 updating, because in the wiring rats-nest that crosses a wire that shares a pull-up between the shift register and the ROM chip...)

    The lesson I'm taking away from this is that noise/crosstalk/signal integrity is a harsh mistress when you're playing with multi-mhz circuits. I'm sure this is going to be super-fun now that I'm about out of excuses to not start working on the RAM interfacing/contention circuitry.
    Last edited by Eudimorphodon; October 29, 2020, 12:04 PM.

    Leave a comment:


  • gertk
    replied
    Originally posted by Eudimorphodon View Post
    ... wait, never mind the above, I realized you were just referring to the hash not leaving a mark.

    In the video it kind of looked like a lot of the dots were offset a consistent distance from the column they were supposed to be in, could this be simply a noise/crosstalk issue? I spent hobby time this weekend rebuilding my prototype to use an AVR 324 instead of a 328 for the timing generator, and after neatening up the wiring I have significantly reduced “jailbar” interference, but that’s let me notice some individual flickering dots. What’s interesting about them is their locations are pretty consistent and I can make them go away by resting my hand on the data bus wires; it’s like certain magic combinations of address and data bus conditions can add up to enough noise to trigger a glitch.
    Yes I was thinking about interference also but the only way I could influence the corruptions is by laying my fingers on the pins of the buffer and/or latches and squeezing hard.
    Viewing the signals with the oscilloscope they are nice and square.

    My guess is that the write timing is too critical. Since the SRAM /WR pulse is generated by the PIO's BRDY signal and this also switches the outputs around from the counters to the latches, the moment the SRAM /WR rises the address latches and databuffer also leave the SRAM address- and databus and the counter outputs take over again.
    According to the datasheet of the SRAM the write hold time can be as short as 0 ns so in theory it should work.

    Another possibility is that the latches are too slow (74HC573) and the address they provide is not stable as the SRAM /WR pulse is released.

    The length of the BRDY pulse from the PIO (with BSTB and BRDY connected together) should be one clock cycle (200 ns as my CPU is clocked at 5 MHz at the moment but switching it back to 2.5 MHz makes no difference, in the circuit diagram it is difficult to see if the PIO and SIO chips are also clocked from the same source as the CPU, have to check with the oscilloscope.

    If not reading or writing the SRAM through the PIO the screen is rocksteady, never misses a pixel, in fact I only reset both counters at once on the vertical sync and there are no weird byte shifts or such per line.


    I will try to replace the latches with edge triggered 74HC574 or 74F574 instead of the transparant 74HC573 latches I have in there now, if no succes I will hook up the Salea16 logic analyzer to the board and see what is going on...

    Leave a comment:


  • Eudimorphodon
    replied
    ... wait, never mind the above, I realized you were just referring to the hash not leaving a mark.

    In the video it kind of looked like a lot of the dots were offset a consistent distance from the column they were supposed to be in, could this be simply a noise/crosstalk issue? I spent hobby time this weekend rebuilding my prototype to use an AVR 324 instead of a 328 for the timing generator, and after neatening up the wiring I have significantly reduced “jailbar” interference, but that’s let me notice some individual flickering dots. What’s interesting about them is their locations are pretty consistent and I can make them go away by resting my hand on the data bus wires; it’s like certain magic combinations of address and data bus conditions can add up to enough noise to trigger a glitch.

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by gertk View Post
    Hope you can see this video: https://www.youtube.com/watch?v=_fJVwtxcsWM

    The hash is quite visible when hammering the read/writes but it causes no permanent corruptions.
    Huh. So when you so "no permanent corruptions" do you mean the offset/extra dots that are appearing between the vertical "pinstripes" don't read back as incorrect if you read the memory contents back? (Because they do seem to be stable on the screen.)

    Leave a comment:


  • gertk
    replied
    Still struggling with the weird stray pixels and corruptions.
    When I write horiziontal lines almost no corruption happens, when writing vertical lines stray pixels appear at random places.

    Hope you can see this video: https://www.youtube.com/watch?v=_fJVwtxcsWM

    The hash is quite visible when hammering the read/writes but it causes no permanent corruptions.
    Last edited by gertk; October 27, 2020, 02:07 AM.

    Leave a comment:


  • gertk
    replied
    Small update:

    I noticed that the 79th column of my graphics overlay only displayed the leftmost pixel. Seems the horizontal sync signal I used for blanking starts at the beginning of the character..
    By using the horizontal sync signal from pin E2 it now displays the 79th column correctly but als column 80, 81 82 etc.. up to the end of the screen...
    Not a real big problem as you can simply wipe those bytes and then it is fine.

    The 1010101 dot patterns which sometimes occured on the far left side are gone now.
    Still I am getting minor corruption on random places on screen during writes and can not lay my finger on those.
    I reprogrammed the GAL to also emit an /OE signal for the ram hoping it might help but it made no difference.

    The graphics video on/off is now done by an additional logic equation on the reset of the shift register and works fine freeing up an output pin on the GAL (now used for the /OE of the RAM)

    The inversion of the graphics output of the shift register is now done by the unused NAND port of U15 (lifted pins 1, 2, 3 and 6 from the socket, video from the graphics board enters on pin 1+2 and pin 3 is connected to pin 6 for mixing with the original Kaypro output)

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by gertk View Post
    The VGA card asserted the /WAIT line too late for the Z80 to act upon (especially during writes). The circuit now asserts the /WAIT line almost immediately after /MREQ and holds it for the first cycles.
    After the circuit has taken /WAIT low, the VGA card itself takes the /WAIT over until the memory access is done.
    Huh. Looking at an ISA reference it says "Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read or write command". I guess the important part there is the "and an active read or write command"; looking at the graphs for a Z-80 bus cycle the Z80 on a read cycle asserts READ at the *same time* as MREQ, while the ISA bus timing does show IOCHRDY not coming until after the read/write pulse starts. So I guess always pre-emptively toggling the insertion of a WAIT on decode is indeed what you'd have to do to be sure when adapting an ISA device.

    Thanks you for this, I was looking for some practical examples of how to do WAITs on the Z80.

    Leave a comment:


  • gertk
    replied
    Some years ago I connected an 8 bit ISA VGA card to a Z80: http://kgelabs.nl/?p=147
    Needed a special 'initial wait state generator' to get the memory access right (see the handdrawn circuit on that page above)

    The VGA card asserted the /WAIT line too late for the Z80 to act upon (especially during writes). The circuit now asserts the /WAIT line almost immediately after /MREQ and holds it for the first cycles.
    After the circuit has taken /WAIT low, the VGA card itself takes the /WAIT over until the memory access is done.

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by gertk View Post
    Since the dotclock is not fed into the GAL it would be tricky to rely on the GAL to generate the load for the shift register.
    Yeah, I wasn't thinking of having the GAL generate the load, just mute it if you're not in the blanking area, IE, psuedocode:

    /SRLOAD = /BLANK * /DCTC

    Where "blank" is whatever combination of conditions that say you're on an active section of a line... but, actually, how you're doing it with holding clear is probably better. The thing that actually pushed me over into generating the LOAD signal with the GAL on my design is I was having some spurious issues after I added the "low-res" clock divider that looked like issues with the LOAD signal registering, and I *think* the culprit may have been the propagation delay added to the pixel clock was causing it to "miss" the load signal going direct from the timing. Whatever it was generating the load signal on a counter again directly in phase with the pixel clock cleaned it up. I suppose there's a chance if you gated LOAD on the GAL it would put the shifted pixels slightly out of register with the Kaypro's pixels?

    For reading you could do the same, it just takes two accesses: one for setting the address and the second for reading the data. That is what is happening with my board also since the /ENA pulse is happening after read from the PIO, and the data is thus latched too late, a second 'IN' instruction then reads the PIO latched data.
    I was planning to make my board straight memory-mapped (although there will probably be a page register so it doesn't actually take a full 12k+ of linear address space, at least unless you want it to), so I don't have the PIO load cycles to get a jump on the memory addresses. Pretty much stuck with techniques that work inside of a single memory read/write cycle.

    Something that's crossed my mind is maybe having some kind of "state machine" based on the SR load counter that would present a wait state on video memory access if it happens within, say, 3/4's of the character cycle leading up to the shift register load, but open it up for a couple bits immediately after the load has been latched. I need to sit down with a piece of paper and compare the machine state timing of the Z-80 with a cycle like that and see if that would leave useful windows long enough for the Z-80 to shove in a read or write and finish with enough time for the address bus to switch back to the "CRTC" and settle to get a clean pixel output for the shift register. Depending on the ratio between CPU speed and character timing I have a feeling it might just end up synchronously sampling T-states during the "wrong" period and ride to the end of the active line anyway, making it the same as the Model III's wait-for-blank method.

    (At 12mhz there's an odd number of pixel clocks per line with my timing, so drifting in and out of "register" would be a real possibility too.)

    On the Acorn Atom the video is also not synchronized to the CPU (and they used a 6502 and an 6847 which can do that perfectly!) and with the games they just waited for the vertical blank to appear and then read/write the screen data. Outside that area there was also 'snow' on the screen.. Alas a lot of CPU cycles were lost..
    I vaguely recall the early versions of the Commodore PET used memory too slow for the 6502's lockstep to work, so they had a vertical refresh interrupt that they intended all screen updates to happen during. (Which means they hash if you write directly to the screen.) But later ones did the timing sync thing?

    Pictures look very nice, and yes you can do some real magic with those GAL's but I often run out of outputs...
    Doing things like counters in GALs makes me realize it's probably time to suck it up and try a full CPLD. It's kind of a bummer there aren't any "internal" registers, if you want a counter you lose an output for every bit. :P

    Leave a comment:


  • gertk
    replied
    Originally posted by Eudimorphodon View Post
    ... I was about to say I'm still a little confused, but I think I get it? I was about to say the datasheet I have for the '166 seems to indicate that when you hold "clear" the output at Qh is low, so that shouldn't really be any different than if clear isn't held low and the '166 is happily running along clocking out the low states it's getting from pin 1 being grounded, but... in the kaypro I assume the problem is you're still getting the "load" pin toggled and loading random memory contents even when you're out of the active video area, so you're pulling "clear" to squelch that.
    Yes the Kaypro counters keep running and thus /DCTC is also active during the retrace/blanking periods.

    (Would it be any more efficient to make the shift register load switchable on/and/off by the GAL instead of manipulating clear? I guess it probably wouldn't make much difference. At least the takeaway is my scheme should be fine as long as I'm only generating load signals in the active area.)
    Since the dotclock is not fed into the GAL it would be tricky to rely on the GAL to generate the load for the shift register.

    Yeah, I was trying to think at one point if a scheme like that with latches really helped me, but I keep getting stuck on the fact that while you might be able to use one to make *writes* synchronous you're boned when the CPU wants to read from memory; either you take the glitch or you need to generate wait states because you won't be able to preload a read latch for when the CPU request comes in.
    For reading you could do the same, it just takes two accesses: one for setting the address and the second for reading the data. That is what is happening with my board also since the /ENA pulse is happening after read from the PIO, and the data is thus latched too late, a second 'IN' instruction then reads the PIO latched data.


    Since the TRS-80 is one of my design inspirations I was looking at how the Model III de-glitched its display (the Model I didn't), and if I understand its service manual correctly it basically has logic to pull down the WAIT signal for the Z80 if video RAM is accessed outside of a blanking area and holds it until it goes into blank. Worst case that would halt the CPU for 64 character's worth of video output. (IE, it looks like it makes no attempt to make the access hold any more granular than that.) If that's a legit way to go that's easy, I could just implement similar logic that defines "not in blank" by that line that lets the load counter in the GAL run. It does seem like there should be a "smarter" way to do it, though, definitely.

    (Ultimately maybe I don't care about video glitch artifacts as long as I can actually make the memory read/writes reliable, but glitch free would be "nice".)
    On the Acorn Atom the video is also not synchronized to the CPU (and they used a 6502 and an 6847 which can do that perfectly!) and with the games they just waited for the vertical blank to appear and then read/write the screen data. Outside that area there was also 'snow' on the screen.. Alas a lot of CPU cycles were lost..

    Here's a picture of the video output from mine as it stands. I just this week solved a problem with another function I had the GAL for, which was a selectable 2:1 clock divider for the pixel clock so I could do both "high" and low-res modes in hardware. (512 vs 256 pixel; the TRS-80 and some of the S-100 cards I want to be able to emulate had 32 column modes.) Shows high and low res alternately running with the same source bitmap. (With the lower res I can move a 32 bytes "viewport" around on a 64 byte line by adjusting counter offsets.)

    [ATTACH=CONFIG]64175[/ATTACH]
    Pictures look very nice, and yes you can do some real magic with those GAL's but I often run out of outputs...

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by gertk View Post
    Yes, parallel loading the shift register is shifting bit D7 (input H) out first so that way it stays in sync with the 7 bit width scheme. I'm keeping the shift register reset during the blanking (vertical and horizontal) otherwise the data keeps on going for all 128 bytes and I get retrace problems. The serial input can either be tied to ground or Vcc since the shift register never gets to the bit from input A (aka D0)

    To keep the screen from getting overlayed with random data during startup (making the Kaypro's own video unreadable), I keep the video output disabled until 'switched on' by the /VON input.
    ... I was about to say I'm still a little confused, but I think I get it? I was about to say the datasheet I have for the '166 seems to indicate that when you hold "clear" the output at Qh is low, so that shouldn't really be any different than if clear isn't held low and the '166 is happily running along clocking out the low states it's getting from pin 1 being grounded, but... in the kaypro I assume the problem is you're still getting the "load" pin toggled and loading random memory contents even when you're out of the active video area, so you're pulling "clear" to squelch that.

    (Would it be any more efficient to make the shift register load switchable on/and/off by the GAL instead of manipulating clear? I guess it probably wouldn't make much difference. At least the takeaway is my scheme should be fine as long as I'm only generating load signals in the active area.)

    I was wondering about the less-than-8-bits thing because I'm thinking of trying to do a VGA output version, but because of the limits on how fast I can clock the CPU I'm using instead of a discrete timing chain I might have to do six bit wide characters instead of eight. (Right now I'm doing a 512x192 effective pixel area on composite with the 12mhz clock, I was thinking with a 20mhz clock, which is the limit without overclocking, I could do 384x192 (triple-scanned) using the exact VESA timings for 800x600@60hz, which uses a 40mhz clock.) I'll need to reprogram the GAL magic that generates the loads to reset the counter at six bit intervals instead of free-running and just rolling over...

    Arbitration is the hardest part. You need either a synchronous system of video and CPU (as can be done with the 6502 for example: first half of the CPU clock is video access, second half is VIDEO access) but with a Z80 you either have to add waitstates or use some other clever technique.
    Yeah, I can definitely see why the home computer makers loved the 6502 so much. Slave the CPU to the pixel clock and the job's done for you. Alas I'm more interested in this phase targeting S-100 and TRS-80-like Z-80 applications.

    I have thought of the following:
    The CPU writes data and address to some latches and then the video circuit handles the writing (synchronously with the character clock)
    With a fast SRAM chip this should be doable.

    You have a 12 MHz dotclock and it gets divided by 8 for your character clock so your time per character access is 1.5 usec. By using the 'other edge' of that character clock you could write the data from the latches into the SRAM without disturbing the reads (which would happen on the leading edge of the clock). If the CPU has an access time of less than 1.5 usec there would be no contention. If the CPU is faster you could add fixed time as waitstate for the video memory range (or uses some NOP's before accessing the video ram again)
    You do need a flipflop set by the writing of the latches by the CPU which indicates that writing is needed, and is reset by the actual write by the video circuit.
    Otherwise the video ram will be filled with the same data over and over...
    Yeah, I was trying to think at one point if a scheme like that with latches really helped me, but I keep getting stuck on the fact that while you might be able to use one to make *writes* synchronous you're boned when the CPU wants to read from memory; either you take the glitch or you need to generate wait states because you won't be able to preload a read latch for when the CPU request comes in.

    Since the TRS-80 is one of my design inspirations I was looking at how the Model III de-glitched its display (the Model I didn't), and if I understand its service manual correctly it basically has logic to pull down the WAIT signal for the Z80 if video RAM is accessed outside of a blanking area and holds it until it goes into blank. Worst case that would halt the CPU for 64 character's worth of video output. (IE, it looks like it makes no attempt to make the access hold any more granular than that.) If that's a legit way to go that's easy, I could just implement similar logic that defines "not in blank" by that line that lets the load counter in the GAL run. It does seem like there should be a "smarter" way to do it, though, definitely.

    (Ultimately maybe I don't care about video glitch artifacts as long as I can actually make the memory read/writes reliable, but glitch free would be "nice".)

    Here's a picture of the video output from mine as it stands. I just this week solved a problem with another function I had the GAL for, which was a selectable 2:1 clock divider for the pixel clock so I could do both "high" and low-res modes in hardware. (512 vs 256 pixel; the TRS-80 and some of the S-100 cards I want to be able to emulate had 32 column modes.) Shows high and low res alternately running with the same source bitmap. (With the lower res I can move a 32 bytes "viewport" around on a 64 byte line by adjusting counter offsets.)

    hi_res_low_res.jpg
    Last edited by Eudimorphodon; October 18, 2020, 03:51 PM.

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