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Can CP/M possibly work on this

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  • Can CP/M possibly work on this

    I've been working on a 8080 emulator using an ATMEGA1284 which has a surprising amount of SRAM for an AVR - 16K. So far I've been able to keep the internal memory usage to below 1K with enough stack room so that 15K of this can be exposed for emulator use (0x0000-0x3BFF). It seems like CP/M 2.2 came configured for a 20K system, so while my SRAM is well below that (15K), I do have flash available. In fact I have 3 banks of 32K flash I can map to 0x8000-0xffff easily. For drives I have two 128K i2c EEPROM which have a very convenient 128 byte page size. Can CP/M 2.2 run from ROM? Certainly some SRAM at the top of the range (under 0x3C00) would have to be used for tables and such, but if only the things that had to be put in RAM were put in RAM. I'm guessing the BDOS pointer at address 5 could be pointed to this SRAM showing programs how little memory they have and it could JMP to flash. Maybe it is a crazy idea, but I wonder if it could be done.

  • #2
    You should be able to move the BIOS and BDOS to high memory flash, and run it "in ROM", leaving the 15K of actual RAM for the TPA and housekeeping.

    I'm pretty sure the meat of CP/M is "rommable".

    You will have to tweak the cold start sequence, since part of its job is to reload that stuff.

    Comment


    • #3
      The tricky part will be extricating "data" locations from the code. CP/M is generally written to run in RAM, and so variables and data are interspersed with code. DRI did make a special version for CP/NOS that is designed to run in ROM, with data separated out. But, that is not a full BDOS with disk I/O so it won't do what you need.
      - Doug

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      • #4
        Originally posted by durgadas311 View Post
        The tricky part will be extricating "data" locations from the code. CP/M is generally written to run in RAM, and so variables and data are interspersed with code. DRI did make a special version for CP/NOS that is designed to run in ROM, with data separated out. But, that is not a full BDOS with disk I/O so it won't do what you need.
        This is further complicated by the fact that much of CP/M depends on pre-initialized variables, so when converting to ROM+RAM you have to add code to initialize all the RAM variables that CP/M expects to have pre-set values.
        - Doug

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        • #5
          You can probably fit the CBIOS in 1K by offloading functionality to the host emulator's flash.

          You may get CP/M to boot in the remaining space, but the question is "what can you possibly do with it?". Given that the result isn't going to be a speed demon, you might want to use an external SPI SRAM for user memory--you'll have more memory than you need for a very small price. Or, you can use an AVR with external memory pinout, such as the ATMega256 or ATMega162 (DIP) and interface your own additional SRAM. I've done it using commodity 128KB SRAM.
          Last edited by Chuck(G); February 17, 2021, 10:25 AM.

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          • #6
            Originally posted by durgadas311 View Post
            This is further complicated by the fact that much of CP/M depends on pre-initialized variables, so when converting to ROM+RAM you have to add code to initialize all the RAM variables that CP/M expects to have pre-set values.
            Well since the full source of CP/M is available you can work out where the embedded data is and separate it, and you can set up those pre initialised variables in your cold boot sequence.

            I'm not sure if it's doable on your proposed hardware - it should be - but I know it's been done before; for example, the Epson PX-8 which runs a cut down CP/M with a microcassette tape based BDOS. Astounding, really... just shows you what you can do.

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            • #7
              Yes, it is absolutely *possible*. One just has to decide if it is worth the effort.

              What CP/NOS did was to switch to using RMAC and separate out data into DSEG (and code/initialize data in CSEG). The data in DSEG has to all use DS pseudo-ops, since the contents of RAM cannot be pre-determined. Then, the cold-start code for each component needs to either copy blocks of initialize data from CSEG to DSEG, or else stuff initial values (e.g. constants) into DSEG. Then, use LINK to combine the REL files, and special arguments to control where the CSEG and DSEG are ORGed.
              - Doug

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              • #8
                I got the picture that it wouldn't necessarily be easy. Maybe easier since there is CP/M assembly source code that could be looked through and modified.

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                • #9
                  Why opt for such a 'small' microcontroller when nice alternatives like the Teensy 4.0 are available? Lots of Flash and RAM and a tiny footprint.
                  I managed to get a Kaypro emulator running with (for now) two floppy drive images on SD-card (the SD card slot is part of the LCD display)
                  80 columns on a 3.5 inch LCD (480x320) and USB keyboard support. I also added a TTL to RS232 converter to have an extra 'real' serial port.

                  Programmed from within the Arduino IDE

                  Teensy_Kaypro_Emu_small.jpg

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                  • #10
                    Looks pretty sweet gertk! What type of display is that?

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                    • #11
                      Originally posted by alank2 View Post
                      Looks pretty sweet gertk! What type of display is that?
                      The display is a:

                      3.5inch 480x320 SPI TFT LCD Serial Module Display Screen Touch Panel IC ILI9488 (eBay)

                      It is a full color RGB display, I have made some hooks in the software to set individual pixels in color, the emulated Kaypro text output is set to green only.

                      The Teensy 4.0 has DMA mode SPI so the screen updates are quite fast, I used software SPI for the SD card reader.

                      Comment


                      • #12
                        Originally posted by gertk View Post
                        Why opt for such a 'small' microcontroller when nice alternatives like the Teensy 4.0 are available? Lots of Flash and RAM and a tiny footprint.
                        I managed to get a Kaypro emulator running with (for now) two floppy drive images on SD-card (the SD card slot is part of the LCD display)
                        80 columns on a 3.5 inch LCD (480x320) and USB keyboard support. I also added a TTL to RS232 converter to have an extra 'real' serial port.

                        Programmed from within the Arduino IDE

                        [ATTACH=CONFIG]66737[/ATTACH]
                        Why opt for such a 'small' microcontroller..?

                        Because it is harder and thus more challenging, perhaps. Or maybe it's what the OP had to hand.

                        Comment


                        • #13
                          I just love the 8-bit AVR series the most which is the reason why!

                          Comment


                          • #14
                            You might want to take a peek at a very cute project by rhkoolstar on retrobrewcomputers:

                            https://www.retrobrewcomputers.org/d...star:cp-mega88

                            He used a ATmega8820AU with external ram. About $4 of parts to run CPM2.2 or CPM3.0

                            I have lots of extra pc boards if you want to give it a try.

                            Comment


                            • #15
                              Originally posted by alank2 View Post
                              I've been working on a 8080 emulator using an ATMEGA1284 which has a surprising amount of SRAM for an AVR - 16K.
                              I have done this on an ATmega8515 myself, using an external 32 KB SRAM. It is possible to have the CPU core live exclusively within the CPU registers, freeing all of SRAM (minus a few bytes for the stack).

                              Originally posted by alank2 View Post
                              It seems like CP/M 2.2 came configured for a 20K system, so while my SRAM is well below that (15K), I do have flash available.
                              Officially, CP/M 2.2 requires a 20K system (CP/M 1.4 requires a 16K system). However, how useful is such a system? I assume that most applications won't run; even more so if you configure for a 16K system. CP/M itself cannot run from read-only memory.

                              You would need to provide your own implementation of CP/M. This can certainly be done, but requires a lot of work. Alternatively, you could ditch CP/M completely and implement the BDOS functions on the AVR side. This is how some CP/M emulators for the PC work. However, even a full 16 KB SRAM won't be enough for most applications.

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