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Build your own PDP 8I, Part 2..

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    #31
    Hi All;
    RAL and RAR Fail..

    Address 0000 Data 7010
    Address 0001 Data 5000

    I seem to have RAL and RAR fixed, I did three things, of which any of them could have solved the problem, none of which solved the problem or any one of them could have solved the problem..
    When I had the board turned over, I one reconnected the wire I took off of the OPG1.L , I had been using a wire jumper.. Two, I found a strand of bare wire in the layers of wires, and removed it.. And three I wired in next to G12 a four pin connector, so I could choose between, no inverter, one inverter, or two inverters, I have it currently set for two inverters..
    Next is the SZL command..

    THANK YOU Marty
    Last edited by Marty; June 3, 2015, 11:25 AM.

    Comment


      #32
      Hi All;
      I'm on a slightly different vein, I am copying more from the Lab manual into my Notebook, I know I could just look at the file, but copying it puts it in my mind and where as reading it, would be like skimming over it.. So, I copy it for my own good..
      I am then next going to see if by doing each equation that I can see, whether the results I want or need is what is showing up.. This will also help me make sure that what I have is correct.. As a for instance in one wire list signal A0 is listed and in the other it is not.. I need to determine which is correct.. Also, even though I seem to have ISZ working, it is working with a change in the circuit, and until I can prove that the change is necessary, I want to check it out..

      THANK YOU Marty

      Comment


        #33
        Marty,

        Have you looked at the charts on pages 9 & 10 of the http://bitsavers.informatik.uni-stut...ings_Dec71.pdf prints?

        If you haven't, it might give you some ideas of how the modern 8/I needs to behave.
        Member of the Rhode Island Computer Museum
        http://www.ricomputermuseum.org

        Comment


          #34
          Hi All;

          M-Thompson, Thank You very much for this Link I never knew of its existence.. It's Great when someone in the know, can point to some Helpful Document or information..
          I will look it over, and try to make some sense of it.. Plus, I can look over the original circuitry for the 8i and see how they did something..
          On page 76 of the PDP 8i clone (Lab Manual) there is a nice description of what my machine is supposed to do.. Which I can check it against what is actually happening..

          THANK YOU Marty
          Last edited by Marty; June 5, 2015, 05:07 AM.

          Comment


            #35
            Marty,

            Can you provide a link to the lab manual? I found a partial manual for the LD20 but not the LD12.

            Thanks,
            Jack
            Jack
            www.computerarium.org

            Comment


              #36
              Originally posted by m_thompson View Post
              Marty,

              Have you looked at the charts on pages 9 & 10 of the http://bitsavers.informatik.uni-stut...ings_Dec71.pdf prints?

              If you haven't, it might give you some ideas of how the modern 8/I needs to behave.
              Those charts took me back quite a few years to my days as a Computer Science student at FIU. In our mathematics & software focused course track we were exposed to Discrete Mathematics and Boolean Algebra to become (hopefully) comfortable with the kind of equations Marty has been going over. In Structured Computer Architecture we developed equations like those and then turned them into chains of gates that were a logical representation of the computer we were tasked to design. Other students who were in the hardware track took those logical gates & turned them into circuit boards that implemented the equations we had developed.

              In every step we were reminded of the Computer Science version of Murphy's law, that implementation of any process or design introduces the probability of error. I bring this up to point out that the lab notes that Marty is working from very likely have errors, as will the two editions of the book. As he wires from the notes he will likely introduce more errors. It's going to be a pain in the neck to determine whether the unexplained behaviors his machine shows are the result of incorrect design, incorrect documentation of the design, or incorrect implementation of the design. As he works through the process and makes changes to the design and his notes this introduces the possibility of even more errors. I'm not throwing rocks at Marty. I think the work he's doing is amazing. It's just that there's no way he's going to avoid the side effects of working with something produced by other error prone humans, being human and error prone himself, and the backlash of the Halting Problem. Be advised that if you read the wiki at the following link your brain will likely hurt for some time.

              http://en.wikipedia.org/wiki/Halting_problem

              In short there is no way to mathematically prove any non trivial system is error free. Any attempt to do so (diagnostic programs and/or test fixtures) will only push the likelyhood of error back another level into the test system. The nature of the beast demands that System B created to test all possible states of System A must be more complex, and therefore more likely to have errors itself. Yet we can create tools that make the steps in the design & build process easier and expose some of the more obvious errors. One that we used years ago was a virtual breadboard that we could populate and wire in a computer to test that our logic at least implemented our equations correctly. I believe it was "LogicLab Explorer". A web search shows a number of more evolved programs, some of them free, that do what LogicLab did and more. It would probably help if someone was to run the equations that Marty is working from through such a process so he could at least have some confidence that the specs he's wiring from are correct or somewhere close to it.

              I'm a rank beginner at most of this stuff, so I'll shut up now and see if some of "The Big Boys & Girls" will give us their thoughts on whether modeling the design of any or all of the LDnn designs on some appropriate test environment would get everyone to a prototype circuit board faster and/or what the best test environment might be.
              "It's all bits on the bus, Cowboy! It's all bits on the bus!" -- Tom Beck, #1ESS Instructor, Southern Bell Opa Locka Training Center

              Comment


                #37
                Hi All;
                First of all, Jack Thank You for Your Question.. Jack You need to go to page one (1), Posting # 9 Where PBirkel gives a Link to where He has Posted for everyone access to these Files.. Remember You need to Register to get the files..
                IF you are Looking in the Book, as I have stated many times before You are Looking in the Wrong Place, the Equations are NOT the same !!

                DDS, Thank You for the Long tomb of Encouragement.. I have thought and sometime either when I have time or It shows I really need to, I will put these down into TTL equivalent equations and Run them through a Simulator.. I can't think at present the name of the Language I would use, but it is a common TTL equation Language.. (VHDL) And Run it as though I was putting it into an FPGA even though I (at present) would not be actually running it in any of the FPGA Boards that I have.. I do have a Digilent (Xilinx) Spartan 3E Startup Board among others..
                I have saved Your Link about the Halting problem.. Just quickly looking through it, I can tell, I won't understand most of it.. Thank You..

                THANK YOU Marty
                Last edited by Marty; June 5, 2015, 07:37 AM.

                Comment


                  #38
                  Hi All;

                  I have found something significant, This is only for the instructions that I have tested, as far as I know.. Such as CLA, etc, and also possibly ISZ..
                  I found that when I tested Kyle's Cxx program at Address '0000 it works perfectly and so does the ISZ program.. But, when I tried to run either one of them at address '0020 they failed.. WHY ??
                  Because some time during the first instruction, instead of updating the PC to go to the next instruction at '0021, it instead goes to '0000 !!!
                  So, the PC isn't getting updated, at this point I don't know the why, I just know that is what happens.. I plan on looking into it tomorrow..
                  I have the order of things happening for the regular instructions and now that I think about it, I have it for the ISZ instruction, So, I can look into what the Lab Manual says about the ISZ instruction, and compare what the Manual says to what I am actually getting..

                  THANK YOU Marty

                  Comment


                    #39
                    Hi All;

                    DDS, You said that "" I'm a rank beginner at most of this stuff, "", yet from What You said at the beginning of the posting "" Those charts took me back quite a few years to my days as a Computer Science student at FIU. "" You have alot more Education and Experience than I do..
                    So, If You are a Rank Beginner, than what am I ?? Since I have No Education in this area..
                    "" In our mathematics & software focused course track we were exposed to Discrete Mathematics and Boolean Algebra to become (hopefully) comfortable with the kind of equations Marty has been going over. In Structured Computer Architecture we developed equations like those and then turned them into chains of gates that were a logical representation of the computer we were tasked to design. ""
                    So, You are the Kind of Person who I would Like to have here right next to me Helping me out on this.. And Guiding me through the process..
                    In the Lab Manual for the ISZ instruction, it states..

                    CLK0: MUX = MB, ALU= A+1, MB Load..
                    Get the old effective operand, increment it and store it in the MB register for a Memory Write..
                    CLK1: Issue a Write Pulse to the Memory, wait until the Memory has completed the operation..
                    CLK2: MUX = PC, ALU = A+1, Increment the PC..
                    It seems to do the same thing, no where I put the ISZ program.. I have tried it at Address '0020 and at address '0040.. Modifying thing where needed.. So that eliminates a stuck bit, or something of that sort..


                    THANK YOU Marty
                    Last edited by Marty; June 6, 2015, 12:18 PM.

                    Comment


                      #40
                      Originally posted by Marty View Post
                      Hi All;

                      DDS, You said that "" I'm a rank beginner at most of this stuff, "", yet from What You said at the beginning of the posting "" Those charts took me back quite a few years to my days as a Computer Science student at FIU. "" You have alot more Education and Experience than I do..
                      So, If You are a Rank Beginner, than what am I ?? Since I have No Education in this area..
                      "" In our mathematics & software focused course track we were exposed to Discrete Mathematics and Boolean Algebra to become (hopefully) comfortable with the kind of equations Marty has been going over. In Structured Computer Architecture we developed equations like those and then turned them into chains of gates that were a logical representation of the computer we were tasked to design. ""
                      So, You are the Kind of Person who I would Like to have here right next to me Helping me out on this.. And Guiding me through the process..
                      In the Lab Manual for the ISZ instruction, it states..

                      CLK0: MUX = MB, ALU= A+1, MB Load..
                      Get the old effective operand, increment it and store it in the MB register for a Memory Write..
                      CLK1: Issue a Write Pulse to the Memory, wait until the Memory has completed the operation..
                      CLK2: MUX = PC, ALU = A+1, Increment the PC..
                      It seems to do the same thing, no where I put the ISZ program.. I have tried it at Address '0020 and at address '0040.. Modifying thing where needed.. So that eliminates a stuck bit, or something of that sort..


                      THANK YOU Marty
                      I dug out my text for the Structured Computer Architecture course I mentioned and found some of my registration papers in it. One of them says all students need to certify they've had their shots by 8/29/1986. So my memories of the material are under near 30 years of other stuff in a 60+ year old brain. My suggestions may do more harm than good.

                      That said, the book is "Structured Computer Organization" 2nd Ed by A. S. Tanenbaum. You can get later editions as PDF's online. Chapter 4 covers the processor we built. The newer editions vary the design quite a bit. But they all have stuff like what you need. Like a block diagram. I noticed the document linked to above on a PDP8 doesn't have one. I have no idea if your notes do. But it's very helpful if you can see laid out how the buses and control leads actually handle getting an instruction from memory into the instruction register for example. You're also pretty much messed up without a schematic. If you don't have one then you should make one asap. Now for some fun stuff.

                      You need rock solid power. TTL doesn't like stuff like noise & ripple. You already know that from your PDP11 adventures. I put it here because others will read this and they might not know. You also need a rock solid clock. If your power isn't right and your clock isn't right it doesn't matter much what else is right, it ain't gonna work.

                      On my next suggestion I ran into a wall. I got a trick from a MC68k design book that I've used to good effect on other processors. The author suggested forcing the processor to execute a chain of NOP instructions in an infinite loop so he could monitor the instruction fetching, pc incrementing, and so forth. He did it a rather nifty way. He wired the equivalent bits directly onto the data bus pins at the processor. Takes all the memory and memory buss hardware right out of the picture. If your machine will run NOP's in an infinite loop for say an hour, there's a lot of stuff you've just proven good.

                      Keep in mind the first time I looked at a PDP8 print was today. Ditto for the PDP8 instruction set. No NOP instruction. >.<

                      Perhaps the PDP8 guys can suggest another way to do that.

                      You also have the ability to grab your processor by the nose an make it do stuff other's can't do. Like run it at an effective speed of 0 Hz. Like jam instructions directly into the IR. Look on the schematic of the PDP8 on the "Instruction Reg & Major States" page. On the middle left you see 8 gates with the inputs labeled IR0, IR1 and IR2. Those are the bits coming out of the instruction register. Those are your opcodes in hardware. You can force those 3 bits and watch how the required control signals are propagated downstream (or not).

                      You mentioned the timing diagrams. I'm gonna guess that those CLK0, CLK1, and CLK2 notations are what Tanenbaum calls clock subcycles. In each subcycle the clock leads are used to gate data from one location to another. The timing diagrams say what is supposed to be going where in each subcycle for each instruction. The rest is figuring out what each acronym means. I gather that EA = Effective Address, MB = Memory Bus, IR = Instruction Register. It's important that stuff happens when it's supposed to happen. Not before & not after. Gating garbage onto a bus before the outputs of the bus drivers have settled will cause disaster. That gating is what the clock is supposed to do. In the time I had to look at the PDP8 schematic I couldn't even find the clock circuitry. All of these documents were designed to be used by people who had been trained on the hardware. I'm just not a PDP8 guy and likely will never be one.

                      Durring my checkered career with Ma Bell I once managed a crew that maintained all 31 switches in the Miami-Dade area. One of my best #1AESS techs had never been to any formal training. But he was the kind of guy who would get out the books, put a scope on the problem and get it fixed. He was entirely self trained because he kept at a problem until he learned how it worked, what part wasn't working, and got it fixed.

                      Don't sell yourself short.

                      I have to drop this & put the hard cover back on my truck. Got to take the wife to a week long sailing school. I'll check back with this thread after that. Good Luck.
                      "It's all bits on the bus, Cowboy! It's all bits on the bus!" -- Tom Beck, #1ESS Instructor, Southern Bell Opa Locka Training Center

                      Comment


                        #41
                        Originally posted by DDS View Post
                        ...
                        Keep in mind the first time I looked at a PDP8 print was today. Ditto for the PDP8 instruction set. No NOP instruction. >.<

                        Perhaps the PDP8 guys can suggest another way to do that.
                        ...
                        Sure, from the PDP-8 reference card, first line documents NOP. Basically the operate instruction with no function bits enabled.

                        Code:
                        GROUP 1 OPERATE MICROINSTRUCTIONS (1.2 usec)
                        
                                                                        Sequence
                        [B]NOP      7000  no operation                          -[/B]
                        CLA      7200  clear AC                              1
                        CLL      7100  clear link                            1
                        CMA      7040  complement AC                         2
                        CML      7020  complement link                       2
                        RAR      7010  rotate AC and link right one          4
                        RAL      7004  rotate AC and link left one           4
                        RTR      7012  rotate AC and link right two          4
                        RTL      7006  rotate AC and link left two           4
                        IAC      7001  increment AC                          3
                        IAC      7002  swap bytes in AC                      4

                        Comment


                          #42
                          Originally posted by AK6DN View Post
                          Sure, from the PDP-8 reference card, first line documents NOP. Basically the operate instruction with no function bits enabled.

                          Code:
                          GROUP 1 OPERATE MICROINSTRUCTIONS (1.2 usec)
                          
                                                                          Sequence
                          [B]NOP      7000  no operation                          -[/B]
                          CLA      7200  clear AC                              1
                          CLL      7100  clear link                            1
                          CMA      7040  complement AC                         2
                          CML      7020  complement link                       2
                          RAR      7010  rotate AC and link right one          4
                          RAL      7004  rotate AC and link left one           4
                          RTR      7012  rotate AC and link right two          4
                          RTL      7006  rotate AC and link left two           4
                          IAC      7001  increment AC                          3
                          IAC      7002  swap bytes in AC                      4

                          ROFL!

                          I was in a rush to get ready for a week long trip and grabbed the first web page I found. It had what I "assumed" was a complete list of PDP8 opcodes. I should have known damn well that no engineer worth his salt would design a machine which couldn't "do nothing very fast".

                          Then the NOP loop would involve forcing the IR bits to 7000 and single stepping it a bit to make sure it thinks its properly fetching an instruction, doing nothing very fast, incrementing the PC, fetching the next instruction (not really, we're jamming NOP down his throat) and so forth. You could maybe monitor interesting leads with the tool of your choice. If it looks like all is well when single stepped then let it run. It should still be chasing it's tail when you get tired of looking at it.

                          If it isn't, the list of stuff to look at is small. The basic "puppy dog" fetch & execute cycle involves a minimal subset of your hardware.

                          If it is, you know the drill. Start expanding the "Known Good" by testing unknown hardware and unknown instructions a little bit at a time. There is no part of this animal you can't access with the analyzer/probe/scope of your choice. It's going to be a matter of troubleshooting one fault at a time. But it is very do-able.
                          "It's all bits on the bus, Cowboy! It's all bits on the bus!" -- Tom Beck, #1ESS Instructor, Southern Bell Opa Locka Training Center

                          Comment


                            #43
                            Hi All;

                            Thank You to DDS and to AK6DN for all of the Helpful Hints and Suggestions..

                            DDS, I left a private message for You a few Days ago, Did You See it..

                            Also, As I told Jack, If You want to see the Schematic, You need to go back to posting #9, of this Thread, for a Link to finding all of the material that I have including Schematic and some Flow Charts.. I have more stuff/information in my NoteBooks..
                            I can tell that I will need to Read and Re-read all that You (DDS) has to say for it to sink in..
                            I have Cleared Memory up to Address '0040 where the program resides, and when I have it in Run mode, and it gets to Address '0041, it will Jump back to Address '0000, and work its way back up to Address '0041.. So, at least from address '0000 thru Address '0037, it is acting like it has NOP's..
                            So, I will try putting in Locations '0000 thru '0037, a real NOP (7000), and see if it does the same thing, as it does with "Zero's" (0000) there in the Memory Locations..

                            THANK YOU Marty

                            Comment


                              #44
                              Originally posted by Marty View Post
                              Hi All;

                              Thank You to DDS and to AK6DN for all of the Helpful Hints and Suggestions..

                              DDS, I left a private message for You a few Days ago, Did You See it..

                              Also, As I told Jack, If You want to see the Schematic, You need to go back to posting #9, of this Thread, for a Link to finding all of the material that I have including Schematic and some Flow Charts.. I have more stuff/information in my NoteBooks..
                              I can tell that I will need to Read and Re-read all that You (DDS) has to say for it to sink in..
                              I have Cleared Memory up to Address '0040 where the program resides, and when I have it in Run mode, and it gets to Address '0041, it will Jump back to Address '0000, and work its way back up to Address '0041.. So, at least from address '0000 thru Address '0037, it is acting like it has NOP's..
                              So, I will try putting in Locations '0000 thru '0037, a real NOP (7000), and see if it does the same thing, as it does with "Zero's" (0000) there in the Memory Locations..

                              THANK YOU Marty
                              There's a bunch of stuff on this site that I haven't figured out yet..... Retrieving private messages is one of them. Not that's it's hard. I just have a bunch of stuff on my plate. Like a garage full of "when I'm retired" projects. At some point down the road when this LDnn project jells out a little better I might pop for a circuit board and build one. That's IFF (math speak for if and only if) I manage to work my way through a 5 foot stack of S100 boxen, mostly Compupro stuff, another stack of hopefully compatible 8" disk drives, 3 pdp11's of varying flavors, and an IMSAI 8080.

                              Until then I'll cheer you on & chip in when I have something to contribute that won't completely throw you off the track.

                              Oh ya.... and about 3/4 of a street rod I want to build.

                              Too damn many hobbies.
                              "It's all bits on the bus, Cowboy! It's all bits on the bus!" -- Tom Beck, #1ESS Instructor, Southern Bell Opa Locka Training Center

                              Comment


                                #45
                                Hi All;

                                DDS, Thank You for the Response.. I just suggested where to look for the information, so You could follow along with a Schematic in front of You.. I also have a pile of S-100 Boards, and instead of a Five foot stack of Boards, I think mine is two to three feet.. I have a stack of 8" Floppy Diskettes, that are somewhere in the vicinity of six to eight feet high.. I once had an IMSAI 8080, but I had to sell it.. (Rent).. And as You know I have a few PDP 11xx's around as well..
                                And since, You are not able to read any private messages, I will also mention my Demostration (not working) Step by Step System and Various Dial phones and my Answering Service Switchboard, to switch to my various Dial Phones.. And then there are my Old 1930's ish Philco Radios to work on.. So, Yes there is plenty to keep me off of the Street..
                                "" Until then I'll cheer you on & chip in when I have something to contribute that won't completely throw you off the track. "" PLEASE !!!

                                THANK YOU Marty

                                Comment

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