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Build your own PDP 8I, Part 2..

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    #46
    Marty,

    Since you are having 'fun and games' with the wire-wrapping tool - can I make a suggestion that may make your hardware construction life a bit easier?

    I have downloaded a tool called logisim (http://www.cburch.com/logisim/) and have entered 80% or so of the main logic path for the LD30 (which is pretty similar to the LD20). This has only took me about 3 days or so (and that includes the learning curve for logisim). Simulating your logic in software first may make your life a bit easier (especially if there looks to be errors in the wiring lists you have). Once you have a working software simulation (based on the physical TTL logic chips you will be using) you can then turn your attention to the hardware itself.

    Just a thought.

    I have found a Japanese website at "http://blog.goo.ne.jp/k74181/e/ca6b8d04d032797c8cf3f2498be872d7" where this is partially described - although it contains omissions, errors and is incomplete. Interestingly, it cross-references your thread on VCF!

    Quite happy to share my circuit in a couple of days.

    Dave

    Comment


      #47
      Hi All;

      Dave, Thank You for the information and the encouragement and links..
      As I have not seen, except for what is in either book, circuitry for the LD20/LD30, I would be interested in seeing what You have..
      I have downloaded the program, Logisim and I have looked at the Japanese site..
      "" Interestingly, it cross-references your thread on VCF! "" Somehow I missed that part.. When I get a chance I will look at it further..
      But First, I need to see If I can get Logisim to work here for me.. THANK YOU for the suggestion and Link..
      "" Quite happy to share my circuit in a couple of days. "" PLEASE !!

      THANK YOU Marty

      Comment


        #48
        Hi All;

        Well, I know that it somewhat works.. When I try a ISZ instruction test starting at Address '0041, and it jumps back to Address '0000, when it is in Run mode it works it's way back up to Address '0041.. So it is Incrementing the PC and doing that correctly, since I am using 'no numbers' with that instruction, an AND '0000, I don't know if it is fully working.. Jump and halt work as well.. I need to try some of the other basic Instructions.. Also, I need to look at OPG1 and OPG2 with the Scope, and see what they are doing..
        The NOP Instruction is not working correctly.. I need to make a list of instructions from the Reference Card and check off what works and what doesn't work, and see if any pattern emerges..
        OPG1 and OPG2 work in both .H and .L.. So nothing is stuck there.. TAD doesn't Increment like AND does.. Since the are Similar, I need to find out why..

        THANK YOU Marty
        Last edited by Marty; June 8, 2015, 06:31 AM.

        Comment


          #49
          Marty,

          An upload of my logisim PDP-8 circuit so far (please note that this is a work in progress - much like yours)...

          I will post again with some details.

          There are a few things that I haven't done yet. These are identified on the 'PDP' drawing under the text heading "BODGES!!!"...

          Dave
          Attached Files

          Comment


            #50
            You will need logisim...

            You may also need a couple of libraries for some of the 74 series chips:

            1. logisim_74v1.zip from "http://74x.weebly.com/blog/library-of-7400-logic-for-logisim" for the 74x->74181->74181.circ library.

            2. 7400 series Logisim library from Ben Oztalay (ZIP, uncompressed) from "http://www.cburch.com/logisim/links.html".

            Unzip and copy the unzipped libraries to your logisim directory (along with my PDP circuit). You may need to use the logisim Project->Load Library->Logisim Library... menu to attach the libraries to my circuit properly?

            Drawing 'main' has the front panel and a few buttons for me to test at the moment.

            The remainder of the drawings should be obvious from their names...

            Select Simulate->Simulation Enabled, Simulate->Ticks Enabled and select the Simulate->Tick Frequency to something sensible like 8 Hz.

            Select the 'hand' icon to simulate things (e.g. operate the switch register (one push for ON and a further push for OFF (i.e. a toggle operation)). PCLOAD, MALOAD, MBLOAD, ACLOAD and IRLOAD should load what is in the SWR register into the appropriate register (only the MSB 3 bits of the SWR is loaded into the IR register for the decoded opcode though).

            In simulation mode you can double-click on ICs and 'zoom into them' to see what is going on within the circuit. Light green lines are logic '1' with dark green as logic '0'. Clicking on a group of wires will give the binary and octal representation of the signals contained. I have also added monitoring points in HEX, OCTAL and DECIMAL for the key signals.

            Switching to the arrow enables you to make changes to the logic circuit. I usually disable the simulation when I do this as I have had some 'odd' effects otherwise.

            The EA logic is currently missing - as is the CORE memory and correct handling for the MB register. JAMIR0 is also missing. Next (after fixing these bits) I need to add the microcode sequencer block - which should incorporate all of my 'bodges'. I may have a go at initially incorporating a very simple sequencer to perform a series of microinstructions to test that the architecture implementation logic is as correct as it can be at the moment. 'ROMs' can be loaded from files in the operating system or hand edited - although I have not tried to use this feature yet. RAMS (e.g. the CORE memory) can also be pre-loaded from a file.

            If you look at drawing 'main' you will find a simulation of a keyboard and teletype output device - which I will try and hook up to simulate an ASR33...

            I was doing a bit of debugging with the AC before I zipped it up and posted the circuit. I had (stupidly) wired the AC bits 'backwards'. A few mouse clicks and everything appears to now be fixed...

            Enjoy,

            Dave

            PS: The link to your thread is in "http://blog.goo.ne.jp/k74181/e/5fa67fac65e657ff821c5b6a10894984/?st=1"

            Comment


              #51
              Hi All;

              Dave, Thank You, Wow, It reads like it is alot of Work..
              I will Definitely need to Follow Your Directions to see some results.. And then maybe do my own, once I figure out If Your circuit is same or different than mine.. Let me get things set up and I will let You know what I have running or not running..

              I have not figured out 'How' to make it work, but it look Great..

              THANK YOU Marty
              Last edited by Marty; June 9, 2015, 02:23 PM.

              Comment


                #52
                Hi All;

                Yesterday, I found and changed one wire of the OPG group, that did not seem to make any difference in the running of the ISZ program..
                Today, I have changed out as a group first all of the 7400 Nand Ic's, after changing them out it made no difference.. But I did see a slight difference after changing them Back to the original IC's, (I preserved their order).. I think their was a pin on one of them, that wasn't making good contact.. Also, after that I seem to see a possible heat related problem, after it warms up it runs better..
                I have also changed out and back, the 7402's NOR Ic's and the 7410's NAND's as well, so far No other differences, I have the 7404 NOT Ic's and the 7430 NAND's to do.. If nothing else shows up after that, then I can fairly well assume it it not a Mis-behaving Gate, but more than likely a wiring type of problem or an implementing of the Logic problem..
                Where LogicSim or something similar would then be needed to ferret out which type of problem is the culprit..

                THANK YOU Marty

                Comment


                  #53
                  Hi All;

                  I found something.. It runs the ISZ program NOW !!
                  One or more of the 7430's is Bad..
                  One or more of the 7474's is Bad..
                  I haven't check which one(s) it is, for now i'll leave it, and check some other programs..
                  Of the toggle in program, that I have for Group 1 instructions, Pass..
                  Of the toggle in program, that I have for Group 2 instructions, SZL, SNA, SKP and SMA Fail..
                  Of the toggle in program, that I have for Group 2 instructions, SZA, SNL, and SPA Pass..
                  I don't know the correlation of these instructions, maybe getting one to work, might get others to work as well..
                  I am rechecking all of the groups of Ic's again, to see if any of them make a difference with the SZL instruction..

                  THANK YOU Marty
                  Last edited by Marty; June 12, 2015, 08:46 PM.

                  Comment


                    #54
                    Hi All;

                    I replaced many/most of the IC's, with very little difference..
                    When Replacing a couple of the 7402's I did get it to work.. For a little while It worked, later I got it to work replacing a couple of the 7400's with a faster part..
                    So, it might/maybe be a timing situation, Part of the reason I am just replacing parts, is I don't know where the Logic for the Skips instructions is located.. It isn't pointed out in the Schematic's..

                    THANK YOU Marty

                    Comment


                      #55
                      Hi All;

                      By looking in the Book, for the skip instructions, I found where the instructions are implemented in my schematic's, as they are both the same..
                      I am going to move one gate from another 7400 to the one for the the skip instructions, that way all four of the NAND gates are on the same chip.. I can then see if changing its speed helps..
                      I found that there are two sets of gates, the first has been moved, now for the second gate..
                      My second gate has been moved just fine..
                      I have tried a couple of experiments, and the sum of them makes No sense..
                      I can pass the following two sets of codes separately, but together they fail..
                      First program, Passes
                      Address 0200 Data 7300 CLA,CLL
                      Address 0201 Data 7440 SZA
                      Address 0202 Data 7402 HLT
                      Address 0203 Data 5200 JMP to 0200
                      Second program. Passes
                      Address 0200 Data 7300 CLA,CLL
                      Address 0201 Data 7430 SZL
                      Address 0202 Data 7402 HLT
                      Address 0203 Data 5200 JMP to 0200
                      Third program, Fails
                      Address 0200 Data 7300 CLA,CLL
                      Address 0201 Data 7440 SZA
                      Address 0202 Data 7402 HLT
                      Address 0203 Data 7430 SZL
                      Address 0204 Data 7402 HLT
                      Address 0205 Data 5200 JMP to 0200
                      Fourth program, Passes
                      Address 0200 Data 7300 CLA,CLL
                      Address 0201 Data 7440 SZA
                      Address 0202 Data 7402 HLT
                      Address 0203 Data 7300 CLA,CLL
                      Address 0204 Data 7430 SZL
                      Address 0205 Data 7402 HLT
                      Address 0206 Data 5200 JMP to 0200

                      THANK YOU Marty
                      Last edited by Marty; June 15, 2015, 10:52 AM.

                      Comment


                        #56
                        I have the first major 'cut' of my LD30 (microcoded PDP-8i) running inside of LOGISIM.

                        I have just finished a RIM/BIN converter for converting paper tape images to a format that can be directly loaded into the RAM module of LOGISIM - so I am able to load in MAINDEC-8i Instruction Test #1. I am currently debugging my processor and have so far fixed a few silly errors (like holding the LINK flip-flop in reset!).

                        Currently baulking at 'TAD TEST 13' where it doesn't seem capable of executing TAD K4000 followed by TAD K4000 to give an AC of 0000 and a LINK of '1'. I shall debug that tomorrow evening...

                        I will get MAINDEC-8i Instruction test #1 running properly and then post my logic diagram and microcode whilst I move on to test #2.

                        The major things not implemented at the moment is the IOT instruction in general and the ability to HALT the processor execution and single-cycle it - but Rome wasn't built in a day! Learning an awful lot about the PDP-8 instruction set though!

                        Dave

                        Comment


                          #57
                          Marty,

                          Just been thinking about your 'random' problems.

                          What are you doing with the unused inputs of the ICs? Are you tying them high or low to prevent random noise from affecting the logic? Tying them low works (but has the side effect of drawing ten times or so more current than pulling them high). Depending on the IC family you are using (I see you are using 7400 series ICs) you shouldn't directly tie unused pins to the VCC rail - but pull them high via a 10 kOhm resistor.

                          Are you using adequate decoupling capacitors in your build? It is generally recommended to use one 0.1 uF decoupling capacitor per IC fitted as close to the VCC and GND pins as possible.

                          Dave

                          Comment


                            #58
                            Hi All;
                            Dave, Congratulations on Your progress.. I didn't/don't know how to make it work..
                            "" What are you doing with the unused inputs of the ICs? "" For now they are Floating, but as I determine that it is not needed, then I will tie it to it's neighbor..
                            "" Are you using adequate decoupling capacitors in your build? It is generally recommended to use one 0.1 uF decoupling capacitor per IC fitted as close to the VCC and GND pins as possible. "" For now I don't have any at all, since I am running a very low frequency, about 340HZ.. I have generally not had a problem with doing this..
                            I am also, at this point tying the Button/switches to an R-S Flip-flop, which before yesterday the Buttons/switches were just pulled Low to ground when the switch was pressed.. And this is causing some new problems, so I might need to make the R-S flip-flop into a clocked flip-flop to make it only one clock cycle per button push.. I will need to experiment with some circuits and see how to implement it..

                            THANK YOU Marty

                            Comment


                              #59
                              Marty,

                              It isn't necessarily the processor clock rate, but the rise and fall times of the signals that causes problems. You should follow daver2's recommendation and add 0.1 uF bypass caps to each IC, and pull the unused inputs high.
                              Member of the Rhode Island Computer Museum
                              http://www.ricomputermuseum.org

                              Comment


                                #60
                                Hi All;

                                I have started to put in some Caps, it will probably be about every other Ic, as many of the wire-wrap pins are already fully wrapped.. And the couple of unused pins, I can tie to their neighboring pins..

                                THANK YOU Marty

                                Comment

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