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Build your own PDP 8I, Part 2..

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  • Marty
    replied
    Hi All;

    I've decided to start part 3,

    Here is the Link..
    http://www.vintage-computer.com/vcfo...-PDP-8I-Part-3

    THANK YOU Marty

    Leave a comment:


  • Marty
    replied
    Hi All;

    I have started to wire up LD-8, I cannot wire up LD-9, until I get the 18 pin sockets, for the 16 pin Ic's, and a Cap..
    But, its a start..
    The sockets should be here about Monday..

    THANK YOU Marty

    Leave a comment:


  • DDS
    replied
    "I think You, meant once Externally Sorted and once Internally Sorted"

    Yep.... I was being called to dinner & typing faster than my brain could keep up with.

    I'm going to throw a wild guess out there. Perhaps they started using some sort of CAD software that wanted to rename the IC's after they had already been working on the row & column system. That would give you one name used internally to the CAD program and another name used externally. It's really far out there but I can think of no other context with respect to the rest of what I've seen in the posted material that would answer "Internal and External with respect to what?".

    Leave a comment:


  • Marty
    replied
    Hi All;

    ""
    In your travels through the documentation. did you see any explanation for why the wiring list was presented twice, once "Externally Sorted" and once "Externally Sorted"? Externally and Internally with respect to what? ""
    "" once "Externally Sorted" and once "Externally Sorted"? "" I think You, meant once Externally Sorted and once Internally Sorted..
    Anyway, I have no Idea, That and so many other Questions, we just don't know the Answer to.. And can only guess at..
    My only guess is that one was earlier than the other, or they originally laid out the unit differently then the later unit.. Also, the Book mentions (I think) five other versions, before the book, so this would have been version number four, and (I think) they were encouraged to try different things and try different circuits out, looking for other/better ways of doing things..
    Possibly reading the Lab manual, the Memory Paper and the I/O paper might help, and reading through both books.. But, I doubt it..
    Also, remember that they got their Lab unit and most likely worked thru all of the Experiments on that Board, Wiring and un-wiring after each session.. Then, at the end of the School Year they took it home.. A fully (hopefully) functional PDP 8i clone..
    I don't know this for sure, that they took it home, But, how else would Mark Arnold have been able to keep His Machine..
    Here is a photo of today's progress..

    001.jpg

    THANK YOU Marty
    Last edited by Marty; September 28, 2015, 06:15 PM.

    Leave a comment:


  • DDS
    replied
    "The M16 is the IC designation from the Externally Sorted List, and the A10 Refers to the Internally Sorted List.."

    In your travels through the documentation. did you see any explanation for why the wiring list was presented twice, once "Externally Sorted" and once "Externally Sorted"? Externally and Internally with respect to what?

    Leave a comment:


  • Marty
    replied
    Hi All;

    Thank You, DDS for Your suggestions..

    "" 1. In looking at the parts list in the Assembly manual I noted that of the IC's listed, every one was a plain vanilla 74nn except for one lonely 74Lnn. Nowadays anything that's being created using TTL pretty much defaults to the 74LSnn series. The internet was being difficult about when the 74LSnn series was released. My TI TTL Data Book is second edition copyright 1976 and the 74LSnn parts are in it. What dates I see in the LD12 materials are in 1974. Perhaps the short note in the Lab Manual about devices not yet readily available refers to the 74LSnn family? ""
    I have Plenty of the plain 74xx, so for now until I can get it working, and then try the LS.. At present it is not a speed thing, But, more than likely a TTL Load thing..

    "" 2. Speaking of dates in the LD12 materials, many of the schematics have dates on them. Some like LD12 Schematic.pdf page 5 have many. To me they're suggestive of revision dates. That bothers me because they suggest that bugs were found and fixed and the drawings updated, but nothing tells us what was changed or why. It would be helpful if any bugs or typo's found are documented here or on the nv8em website with the rest of the documents. Any useful information like lead names, IC types and location and pin numbers should be clear enough so that someone else 10 years from now doesn't have to debug this stuff all over again. ""
    I don't remember for sure, whether I have put all that I found here, or not.. I think I did..

    "" 3. There are some notations on the schematics I find puzzling. Referring again to the LD12 Schematic.pdf page 5 lower left corner is a gate, apparently on a 7430 that's also labeled A10. Are these IC's numbered in a coordinate fashion like row and column? If so I'm guessing the A10 inside the gate symbol is the location on the original design. If that's correct, what does the M16 just above the gate refer to? ""
    The M16 is the IC designation from the Externally Sorted List, and the A10 Refers to the Internally Sorted List..

    "" 4. I'm also going to start tinkering around for the first time with Logisim. And I would appreciate it if any corrections you guys find that we and future tinkerers might need be documented here and/or on the nv8em site as well. ""
    I think we can put updates here.. I don't know how to add them to the nv8em site..

    THANK YOU Marty

    Leave a comment:


  • DDS
    replied
    A couple of ideas:

    1. In looking at the parts list in the Assembly manual I noted that of the IC's listed, every one was a plain vanilla 74nn except for one lonely 74Lnn. Nowadays anything that's being created using TTL pretty much defaults to the 74LSnn series. The internet was being difficult about when the 74LSnn series was released. My TI TTL Data Book is second edition copyright 1976 and the 74LSnn parts are in it. What dates I see in the LD12 materials are in 1974. Perhaps the short note in the Lab Manual about devices not yet readily available refers to the 74LSnn family?

    2. Speaking of dates in the LD12 materials, many of the schematics have dates on them. Some like LD12 Schematic.pdf page 5 have many. To me they're suggestive of revision dates. That bothers me because they suggest that bugs were found and fixed and the drawings updated, but nothing tells us what was changed or why. It would be helpful if any bugs or typo's found are documented here or on the nv8em website with the rest of the documents. Any useful information like lead names, IC types and location and pin numbers should be clear enough so that someone else 10 years from now doesn't have to debug this stuff all over again.

    3. There are some notations on the schematics I find puzzling. Referring again to the LD12 Schematic.pdf page 5 lower left corner is a gate, apparently on a 7430 that's also labeled A10. Are these IC's numbered in a coordinate fashion like row and column? If so I'm guessing the A10 inside the gate symbol is the location on the original design. If that's correct, what does the M16 just above the gate refer to?

    4. I'm also going to start tinkering around for the first time with Logisim. And I would appreciate it if any corrections you guys find that we and future tinkerers might need be documented here and/or on the nv8em site as well.

    Leave a comment:


  • Marty
    replied
    Hi All;

    Dave, Thank You for Your Answer, and willingness to enter this in..
    "" I was horrified by the logic for the register loading signals [e.g. MB(L)]. You need to be VERY careful with the type of gate in the /CLEAR side to prevent you getting a very short 'runt pulse' that will not be seen by the registers (or may be seen only under certain circumstances). Are you actually using a 74L00 in this position? ""
    YES, I have a few 74Lxx Ic's, even though with You mentioning it, I think I will put in a 7408, followed by a 74L00, Used as an inverter to lengthen it a bit more.. I will need to see what I have, to implement this /Clear signal..

    "" I agree with DDS - that some of this 'design' looks (and probably behaves) strange... ""
    Any Ironing out You can do, Please let me know about..

    ""I will post my logisim design when I have completed it, ironed out the bugs and it runs some of the diagnostics. ""
    Please post it,before you have Ironed out the Bugs, and I (at least) can see the progression and possibly the "why" of what You are doing or did..

    THANK YOU Marty
    Last edited by Marty; September 28, 2015, 09:34 AM.

    Leave a comment:


  • daver2
    replied
    My - your construction looks mighty nice...

    I have started 'in earnest' entering the schematics into Logisim. As I was doing this - I am coming across all sorts of discrepancies. Some with the Lab manual descriptions of signal derivations, some with how the Lab manual signal derivations are implemented by the schematic etc. etc. etc.

    I am doing the 'simple logic' for now (e.g. the registers and the bulk of the combinatorial logic dealing with the MUX and ALU control signals, decoding of the OPR instruction (group 1 and 2) and register loading).

    I was horrified by the logic for the register loading signals [e.g. MB(L)]. You need to be VERY careful with the type of gate in the /CLEAR side to prevent you getting a very short 'runt pulse' that will not be seen by the registers (or may be seen only under certain circumstances). Are you actually using a 74L00 in this position?

    I agree with DDS - that some of this 'design' looks (and probably behaves) strange...

    I will post my logisim design when I have completed it, ironed out the bugs and it runs some of the diagnostics.

    PS: You don't need a bit slice processor for a microprogrammed design. My LD30 logisim implementation just uses a 7-bit loadable binary counter, some fast ROM and a couple of multiplexers and D-type latches.

    Dave

    Leave a comment:


  • Marty
    replied
    Hi All;

    I got some of the Power wiring done last night..

    001.jpg

    THANK YOU Marty

    Leave a comment:


  • Marty
    replied
    Hi All;

    I just got some wire, so now I don't need to use just little pieces of wire, and try to find something long enough..

    Here is a picture of what might be, plenty of room, I hope..

    002.jpg

    I am still working on Placement of the Ic's..
    Placement is done, with some room left over, but not much.. Most rows have a couple of unassigned places..
    Now to wire up Power and Ground..

    001.jpg 002.jpg

    Power and Ground is going to be more difficult than before..

    THANK YOU Marty
    Last edited by Marty; September 26, 2015, 10:50 AM.

    Leave a comment:


  • Marty
    replied
    Hi All;

    DDS, Thank You for Your reply..
    "" Look at "LD12 Schematic.pdf". On page 5 a bit left of center is a chip that counts pulses from the clock and generates the discrete CPn leads for each clock interval CP0 thru CP7. Now look at "Lab Manual.pdf" on page 104 there's a chart showing leads developed for various instructions for each CPn interval. If some of your chips were being enabled earlier or later than they should have been you may have found at least one of the reasons for the flaky results you were getting. ""
    That is exactly where I was looking at ( Lab Manual page 104) .. And I knew about the the 7442 that Generates the CPx signals..
    What I think I will need to do is make another chart that Traces the Wire Listing for each of the CP Signals and compare them to what is on Page 104 of the Lab Manual, and if or what other CP mistakes there might be.. Also, it would be a good Idea to check the rest of the chart against what was wired..
    "" If some of your chips were being enabled earlier or later than they should have been you may have found at least one of the reasons for the flaky results you were getting. ""
    Yes, that would explain alot of what I was seeing, and not knowing where to look.. So, while I am re-doing my Notebook and wire lists, I can check for other misprint mistakes.. And make some more flow charts..

    THANK YOU Marty

    Leave a comment:


  • DDS
    replied
    Originally posted by Marty View Post
    Hi All;

    I found another mistake, that I had previously wired wrong.. But, I didn't know that it was wired wrong..
    On the Ext wirelist, On K12 it shows pin 2 of the 7400 wired to CP5.H, pin 1 goes to IR10.H, pin 3 is therefore IR10.CP5.L and this connects to K3.12, a 7402 K3 pin 11 Halt.L (OPG2.IR10), pin 12 is IR10.CP5.L and its Output is pin 13 OPG2.IR10.CP4..
    What shouldn't that be CP5, well tracing it back and looking at the schematics, the CP5 was Mislabeled and should have been CP4, all along..
    BUT, Looking at the Lab Manual, under LD-3, that shows it should be CP3 !!! And Not CP4 or CP5..
    I think I will need to try all three and see which one works better or more correct..

    THANK YOU Marty
    Look at "LD12 Schematic.pdf". On page 5 a bit left of center is a chip that counts pulses from the clock and generates the discrete CPn leads for each clock interval CP0 thru CP7. Now look at "Lab Manual.pdf" on page 104 there's a chart showing leads developed for various instructions for each CPn interval. If some of your chips were being enabled earlier or later than they should have been you may have found at least one of the reasons for the flaky results you were getting.

    Leave a comment:


  • Marty
    replied
    Hi All;

    I found another mistake, that I had previously wired wrong.. But, I didn't know that it was wired wrong..
    On the Ext wirelist, On K12 it shows pin 2 of the 7400 wired to CP5.H, pin 1 goes to IR10.H, pin 3 is therefore IR10.CP5.L and this connects to K3.12, a 7402 K3 pin 11 Halt.L (OPG2.IR10), pin 12 is IR10.CP5.L and its Output is pin 13 OPG2.IR10.CP4..
    What shouldn't that be CP5, well tracing it back and looking at the schematics, the CP5 was Mislabeled and should have been CP4, all along..
    BUT, Looking at the Lab Manual, under LD-3, that shows it should be CP3 !!! And Not CP4 or CP5..
    I think I will need to try all three and see which one works better or more correct..

    THANK YOU Marty
    Last edited by Marty; September 25, 2015, 06:14 AM.

    Leave a comment:


  • Marty
    replied
    Hi All;

    Dave Thank You for the Explanation..
    "" I was trying to answer DDS about why the Lab notes talk about a 7400 as an AND gate in some places. ""
    OK, that explains it..
    "" Back in post #117 you were asking "I could use an Explanation from Daver2 on A1 thru A9 and on F0 thru F10, to clarify things some..". This was what I was meaning to do. Do you now understand what the Fx and Ax signals do (hence I don't need to provide the explanation any more)? ""
    YES, Please !! Maybe Your explanation, will help me understand about Your answer on the next paragraph..
    "" I don't see why you are going to all the trouble of equalising the gate delays to such things as the ALU? From the register outputs through the MUX and the ALU back to the registers is a combinatorial path (i.e. devoid of clock signals). All that matters is that the data arriving back at the registers is stable just before the clock latches the data back into the registers. It may help if noise is present - but that is more by luck than design.
    Since, before I would get different answers, at different F states and some of the differences, would be the ALU doing one thing at (say) F0 one time and something different at F0 the next time.. So, S0-S3 and M are the same, but Cin is different, and so one time it Increments and another it Passes the contents on..
    I hope that this is as clear as Mud..
    "" Just as a matter of interest - are you using Fairchild 9024 JK flip-flops in your implementation or have you replaced these with an alternative? ""
    A 74109..

    Just for the fun of it, and to stir my clear as muded mind, I am going to Read His chapters in Both Editions on His MicroProgrammed Design..
    I have looked at both descriptions, in each of the Editions of the book, and they are Both different for the most part..
    Though, the Second Edition of the Book is a far better Description of Implementing the the PDP 8i using Bit Slice Ic's, there are alot of holes in its Description, that is much left up to the Reader to figure out..
    It does use Forth on its MicroComputer to implement the code for the Bit Slice Processor..
    So as for me it is and would be far easier to implement the PDP 8i as I am doing, than to do so in/with Bit Slice Technology, because of the added burden of writing and implementing the additional Code and Hardware to make the Bit Slice's work..
    But, Yes once the Supporting code and Hardware are done, then Yes, it would be easier and far less Ic's to implement it using Bit Slice..
    THANK YOU Marty
    Last edited by Marty; September 24, 2015, 03:20 PM.

    Leave a comment:

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