Ensoniq EPS classic repair. 68k cpu

[foofles]

Hello, I'm trying to repair this vintage synthesizer and could use some help.

Tons of technical info on it here http://zine.r-massive.com/ensoniq-technical-documents-and-schematics/

The story so far ...
Replaced the floppy drive with a floppy emulator. The system tries to boot, then displays "Error 18". I managed to get it to boot a couple of times and it made horribly distorted audio.
Pulled all of the 41256 ram chips off and tested them. Found one bad and replaced it. Still won't boot.
I've been poking around with my oscilloscope to see what I can see. Haven't found any address or data lines stuck high or low, but a lot of them do look ... bad. Very noisy. But I really don't know what I'm looking for. Maybe they're supposed to look like this? Attached image is how several address and data lines on the 68k cpu look.

Maybe someone can offer advice on what I could look for with my scope?

 

[foofles]

Looking at A16 now. The only things it goes between is the main cpu and a 74ls373 flip-flop (u41 pin 2 on datasheet). A16 looked bad to me, so I pulled the flip-flop off, but it still looks the same. Note that I am not seeing the chip enable pin active on u41.
Pic attached is of A16 with the flipflop u41 removed, so it's coming from the cpu. The other address lines that go to u41 look the same. On power on, I do see activity on these lines where some things are reaching the proper 5v, but it still has all of these ~3-3.5v spikes in it

edit: testing the flip-flip on a breadboard now. Maybe I dont understand something, but it doesn't seem to be working. But I'm new to this...

 

[cruff]

Looks like possible ground bounce, caused by bad bypass capacitors. Start checking for leaking electrolytic capacitors on the power supply board and poor connections on the power harness connections.

 

[foofles]

Thank you for your reply. I actually recapped most of the psu in the past. There's a single 10uf electrolytic for the 5v rail that was not replaced, but I don't have a replacement on hand. All of the big caps were replaced in the past.

edit: and not all address/data lines look as bad as the ones in the pic

 

[cruff]

Check the 1 uF bypass caps on the main board, such as C49 and C32. You would need to unsolder at least one leg to isolate them to test properly. Are the ICs socketed? If so, gently pry them up a bit and reseat (no need to remove fully from the sockets).

Is the CPU clock at pin 15 running properly at 10 MHz? Switch your oscilloscope probe to the 10x setting to reduce the loading on the circuits you are probing. Also ground the probe as close as possible to the place you are probing to reduce interference. Check that CPU pins 6-10 show regular activity at least for a while after you power on the synth.

 

[foofles]

Sadly I don't have anything with me to test the capacitors except an ohm meter. The resistance never moves from infinite though. I think that's not how it should be? I can get a better meter later that has actual cap tests on it.
The bypass caps are ceramic (I think). Is there some reason to use ceramic vs electrolytic? I do have spare electrolytics laying around


Yeah, I've resocketed all of the chips a few times as well as cleaning the sockets and legs. Probably do need to do it again with deoxit.

Yeah, all clock signals are good. Will double check pins 6-10 in a bit, but I think they were all showing signs of life the other day.

 

[daver2]

Looking at A16 now. The only things it goes between is the main cpu and a 74ls373 flip-flop (u41 pin 2 on datasheet). A16 looked bad to me, so I pulled the flip-flop off, but it still looks the same. Note that I am not seeing the chip enable pin active on u41.
Pic attached is of A16 with the flipflop u41 removed, so it's coming from the cpu. The other address lines that go to u41 look the same. On power on, I do see activity on these lines where some things are reaching the proper 5v, but it still has all of these ~3-3.5v spikes in it

edit: testing the flip-flip on a breadboard now. Maybe I dont understand something, but it doesn't seem to be working. But I'm new to this...

Not quite. U41 actually DRIVES A16. It is an octal latch driven from the data bus on the D inputs and drives the Q outputs when pin 1 (/OE) goes active (LOW).

A16 is used in the address multiplexer chips for the dynamic RAM.

Something writes the 16-bit data bus into the two latches (U41 and U44) to be used (I suspect) by the DMAC ( U28 ).

You can't say for sure what signal looks 'duff' if you don't trigger the scope on some sort of valid memory access. The address bus (for example) could have been relinquished by the 68000 CPU and (therefore) it will either float - or be pulled up via the pull-up resistors on the very left-hand side of the schematic. This will not be a very nice waveform - but an exponentially increasing one (as you have potentially observed).

Dave

 

[foofles]

Not quite. U41 actually DRIVES A16. It is an octal latch driven from the data bus on the D inputs and drives the Q outputs when pin 1 (/OE) goes active (LOW).

A16 is used in the address multiplexer chips for the dynamic RAM.

Something writes the 16-bit data bus into the two latches (U41 and U44) to be used (I suspect) by the DMAC ( U28 ).

You can't say for sure what signal looks 'duff' if you don't trigger the scope on some sort of valid memory access. The address bus (for example) could have been relinquished by the 68000 CPU and (therefore) it will either float - or be pulled up via the pull-up resistors on the very left-hand side of the schematic. This will not be a very nice waveform - but an exponentially increasing one (as you have potentially observed).

Dave

Thanks. That's why I was confused. The octal latch never has OE go low but I was seeing signals on it. I thought it would be steady since those lines have pull up resistors on them?

I'll keep poking around looking to see what I can see. Any suggestions are welcome!

Edit: and U41 that I pulled off does seem bad in a breadboard, but I could be doing something wrong. It seems to output high on Q1 regardless of OE, LE, etc

 

[cruff]

The ceramic caps are used where you don't need a higher capacitance that an electrolytic can supply. The ceramic caps are usually pretty robust, so you probably don't need to worry about them. As daver2 says, the 68440 DMAC chip can also drive the address bus via the latches.

If you have the enable pin of the 74373 pulled high and OE pulled low, the outputs should follow the levels on the input pins. If you drive enable low, the latches should retain the state they had at the point it is driven low. If the other output pins (other than Q1) behave in this manner, then looks like you have identified a bad chip. That could make sense with the distorted audio due to mangled addresses being driven by the DMAC via that latch.

 

[foofles]

I don't really understand why the output of this is only going to an address pin of the 68k cpu. Are the address pins used for inputs at some point?

And I *may* have been doing something very stupid testing these latches. Putting 5v into the ground pin tends to not work quite right.

 

[daver2]

It's not. The output of the (two) latches are going to the address bus itself.

The address bus (and certain control signals) decode for the memory devices (ROM/RAM) and I/O devices.

However, it is unlikely that the 68k CPU itself can keep up with the demands for audio at the same time as doing other things etc. For this, it will offload most of the task of driving the audio interface (be it IN or OUT) to the direct memory access (DMA) device (DMAC on the schematic). The 68k and DMAC share the same address, data and control bus BUT they can't be both driving it simultaneously. They agree between themselves which device is going to access the bus (and it is likely that the DMAC has the higher priority to service the audio stream).

Some DMA devices may be limited to (say) 64K blocks of memory - but the 68k can access a larger memory space. To obtain further address lines, additional address latches are required. These will only be enabled when the DMAC has control of the bus (hence the control signals for the two latches are driven by the DMAC if you follow them).

Under normal operation the 68k will be driving the bus. The 68k will have programmed the DMAC with the parameters for the job in hand (say transferring a block of memory to an audio output device on demand). When the audio device requires some data - it will signal this request to the DMAC. The DMAC will negotiate with the 68k to gain access to the bus at the earliest opportunity. The 68k will finish the instruction it is currently processing and will tri-state its signals and tell the DMAC that it has access to the bus. The DMAC will then perform its job (transferring a byte, word, block of words from memory to the audio device) and will then signal back to the 68k that it can have the bus back. The 68k will then carry on with the next instruction.

When the DMAC has finished its job, it will probably signal this to the 68k via an interrupt. It can then be programmed (by the 68k) for the next task.

So (basically) both the 68k CPU and the DMAC (via the latches) can BOTH drive the address bus - just not simultaneously!

By the looks of it, the specific address line in question is only utilised by the DRAM address multiplexers - but the higher-order address lines from the latches will probably be used to decode the memory spaces etc.

I hope this explanation helps?

Dave

 

[foofles]

Hey, thanks for the info!

I didn't see that these address lines were going to the 253 chips for the dram. It makes sense now.

I've been reading up on what all of these 74 series chips do and trying to make sense of all of this. I'll go back to more poking and prodding and researching after I can get the display board working again. The cables are pretty worn out it seems.

 

[foofles]

I'm back. Had to repair some damaged traces. This board really doesn't like to have things desoldered from it.

I'm looking at the datasheet again, and it looks like only the cpu and the dmac drive A1-4. However, the dmac never has its CS line turned on during this. It only has CS low during a short burst. A2,3,4 are all way worse looking than A1, which has a nice, square waveform.

What could cause this? A1-4 go to other chips, but only as inputs. duart, ram, eprom, ls253's, and an ls244 are all connected to A1-4 as inputs.
Could one of these chips going bad cause it to make the signals I'm seeing all funky looking? Images are of A2 and A3

Edit: should note that I actually do have a spare dmac and that is not the issue

 

[cruff]

Let's check some things about how you are probing the signals to make sure it isn't noise induced into the probe. What type of scope probe are you using? Is it a 1x only or a 1x/10x or 10x probe? Where is the ground lead of the probe connected in relation to the signals you are probing?

 

[foofles]

Probes are 1/10x. Using on 10x. Ground lead is very long. I know it will pick up noise, but I don't think that's what I'm seeing here on A2 and A3. Like I said, A1 is very clean looking. (with a bit of noise from my long ground lead!)

 

[cruff]

Can you also capture the AS signal (pin 6 of the CPU) on another channel? When it goes low, the state of the other address lines should be reasonably stable. Perhaps the spikes on the address lines aren't the main cause of your issue, although it looks like there is significant ground bounce still present.

 

[foofles]

That makes sense.

Here are A1,2,3 plus the AS signal.
Triggering on AS. I hope that's the correct thing to do in this situation.

I also replaced more electrolytic caps before taking these measurements. I don't think there's any left that would affect this.

And also I made the ground loop much much shorter for the probe measuring AS. Still noisy

 

[cruff]

Is trace 1 (yellow) is the address line and trace 2 (pinkish) is the /AS strobe? And I assume they are A1, A2 and A3 from left to right?

The rising levels that appear to be noise on the address lines are being caused by the pull up resistors when they not being actively driven (i.e. when /AS is high). It isn't clear from the short captures if A2 just happened to always be driven low. Obviously A3 is being driven to both levels. You'd might need a logic analyzer with a longer buffer to see if it is being driven to both logic levels, or adjust your scope timebase to capture a longer period of time.

However, the ~0.4 V shifts on the A1 line could be indicative of a problem. It looks like the A1 line isn't reaching the low level correctly, but you might try a few more captures on A1 and A2 to see if you can see they are being driven to both the low and high levels when /AS is low.

 

[cruff]

Something quick to test, see if the value of the pull up resistor for A1 (RP2-3) has a value close to 3.3K. The common pin for that resistor pack may be pin 1.

 

[cruff]

The CS line for the DMAC will only be active when the CPU accesses it to program the DMA transfers and check status registers. When the DMAC is performing DMA, it will drive the control lines like the CPU does, which could result in the CS lines of other chips being asserted.

You may want to change the /AS trigger to the falling edge, which is when it goes active, but that isn't a big deal, it just offsets the display of the captured waveform.

Is anything plugged into the Aux Expansion Connector? What about the Memory Expansion Connector?

Theoretically a chip input can affect a signal line if the chip has failed in a way to short the input to one of the supply rails or another signal. You could try (if the chips are socketed) pulling some that are attached to the address lines and see if it looks better (A1 specifically, unless you are able to determine it is going low). If the DMAC had a bad A1 output, that might give a clue.

Re: damaging the board when unsoldering, do you have access to a vacuum desolder tool? Those make it much easier to reduce the heat transferred to the PCB and traces. Check for possible solder bridges where you have been working on the board.

Heh, thought printing the schematic on 11"x14" paper would be usable, turns out while it is legible, for my older eyes I still need a magnifying lens.