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8 bit IDE (XTA) Replacement Project

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    #16
    Originally posted by Chuck(G) View Post
    If I needed an XTA emulator, I'd build on one of the existing ATA emulators, such as this one using an RPi zero. Doubtless there are others not using a GHz MPU to do the work...
    I was not aware of this project. It is interesting. I can not locate any of the source materials: they do not appear to be released yet. I can not tell whether the implementation boots an OS on the Pi or runs custom firmware. Booting as OS is not what I had in mind - you run into issues with the Pi booting slower than the PC and the Pi getting ungraceful shutdowns.

    It does probably remove the need to design the circuit and layout a PCB. Although that is the part I enjoy the most. I was looking forward to designing a form factor that could be properly mounted in a 3.5" bay by way of a common style of 2.5" to 3.5" adapter bracket. Starting with this Pi project would still require much rework of the FPGA logic and the Pi code but perhaps it does reduce the work some. It would be hard to move forward with the project still in alpha and the source materials unpublished.

    I am not aware of any other hard drive replacement projects that are suitable. I am certainly open to suggestions. The FreHD, while not directly applicable, does set the bar high on component optimization. Just a GAL22V10, serial to parallel bidirectional buffer and an 8 bit micro. Data is clocked directly from the SD card to the serial buffer when applicable. Very clever IMO. I shall endeavour to be as efficient.

    Just before hitting send I did some searching and found the SCSI2SD project. While not directly applicable, it uses an interesting microcontroller/programmable logic combo IC from Cypress. It is a somewhat expensive and unique part to base a design around. But plenty of logic, CPU and 5v support all in one device is very appealing.

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      #17
      Originally posted by Eudimorphodon View Post
      You are aware that an 8088/8086 bus cycle is four clock cycles and that data (in the case of a read or write) isn’t sampled until the third cycle, correct?
      I was thinking that I should hook up a scope with the ST05X card on a fast PC to see what the worst case signal timing looked like. I will do that sometime soon as I think it will be instructive.

      Comment


        #18
        Originally posted by JayesonLS View Post
        Just before hitting send I did some searching and found the SCSI2SD project. While not directly applicable, it uses an interesting microcontroller/programmable logic combo IC from Cypress. It is a somewhat expensive and unique part to base a design around. But plenty of logic, CPU and 5v support all in one device is very appealing.
        Some of the Cypress PSoC devkits are pretty cheap. There's at least one floppy flux sampler built on one with nothing more than a header installed.

        Reach me: vcfblackhole _at_ protonmail dot com.

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          #19
          Originally posted by JayesonLS View Post
          I was thinking that I should hook up a scope with the ST05X card on a fast PC to see what the worst case signal timing looked like. I will do that sometime soon as I think it will be instructive.
          I will definitely be keeping an eye on this thread. I have several vague project ideas on my brainstorm list that would benefit from finding a cheap microcontroller that’s fast enough to do direct port I/O with an old-tymey CPU bus without a lot of glue. In my junk box I have a stash of Blue Pills I bought for experimenting with but they are a big leap in complexity compared to the AVR8s I’ve been using. One nice thing about the AVRs is they can do byte I/O at full clock speed in assembly; ARMs are a lot more… asynchronous.
          My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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            #20
            Originally posted by vwestlife View Post
            For those unfamiliar with them, here's my video about IDE-XT (XTA) drives and interfaces:

            Thank you for posting this reference; very nice video :->!

            Comment


              #21
              Originally posted by Eudimorphodon View Post
              You are aware that an 8088/8086 bus cycle is four clock cycles...
              I was aware that there was a 4 clock timing of the read/write operations although I thought it was based on a clock 4x the CPU clock. I must have misunderstood something when poking around on the Tandy 1000 board.

              I wrote a little test program to do rapid register writes and explored a bit with the scope. I used a 486 DX2/66 with ISA clock set to 33/3. The chipset seems to drop this to 10Mhz by extending some of the cycles. I used this as I expect there will be 10MHz bus clocks on some of the 286 boxes. I have shared one image here, slightly more info is available at https://github.com/JayesonLS/8bit-ide-analysis

              This image is shows about the first 1.5 IO write cycles of the ST05X BIOS code that does 6 rapid writes to port 320 to set the controller command registers. Yellow = CLK, cyan = XTA ~CS, magenta = D0, blue: ~IOW. The scope is not calculating the frequency of CLK well in this image - zooming out a bit seems to give a fairly consistent 10MHz. One interesting thing with the 486 is that the CS gets held low for long periods. I think the address lines do not always get updated on the ISA bus, which I guess makes sense since it is not possible to keep the slower ISA bus fully up to date with what is happening on the CPU bus. One thing I note is that the IO write (and presumably read) cycle seems to be even longer than 4 clocks. It does sound familiar to me that IO cycles are extended.

              I also ran a routine that uses REPNZ OUTSB and the timing is identical on this 486. I think I am going to have to run these tests again on a 286 to see what happens. I do have a Tandy 1000 TL/2 which seems like a good fit other than the 8MHz CPU. Hopefully I will come across a 10MHz 286 XTA PC somewhere along the way.

              Anyway, the data point I was after is that there is 13 clocks between each ~IOW. I was hoping it would be just a little longer but it think it work for what I have in mind. My hardware plan was to use at ATMEGA328 at 20MHz with an external universal shift register to hold the data. And a GAL22v10 to provide some glue. I like this approach as the bill of materials is inexpensive, can be all through hole and anyone with a TL866 can program the chips. Plus the timings on these micros is quite predictable.

              The idea is that on an IO write, the GAL would latch the data into the shift register and signal the ATMEGA there was data. The ATMEGA would then trigger an SPI read. The SPI read would take 8 10MHz bus clocks to get the data out of the shift register, leaving at most 5 10Mhz clocks / 10 20Mhz clocks for the ATMEGA to detect the signal from the GAL and trigger the SPI read. I think it will just work. Especially if there is a requirement to use lower bus clocks if someone, for some reason, wanted to use an XTA card in a fast PC.

              [EDIT] I set the 486's bus clock back to the default 8.33MHz. The period between ~IOW's is still 13 CLK's which gives an additional 5 20MHz clocks to the ATMEGA. I am excited - I think my plan is going to work.

              NewFile2.png
              Last edited by JayesonLS; September 8, 2021, 08:27 PM.

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                #22
                Some of the PIC32 MCUs have a bus interface register, if that helps.
                Reach me: vcfblackhole _at_ protonmail dot com.

                Comment


                  #23
                  Good luck with this interesting project, I hope it'll be completed successfully.
                  Out of curiosity, does it cover a need/scenario were the XTIDE cards cannot be used? Or are you trying to provide an actual XTA drive replacement, even thought the XTIDE cards are an alternative?

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                    #24
                    Originally posted by konc View Post
                    Out of curiosity, does it cover a need/scenario were the XTIDE cards cannot be used? Or are you trying to provide an actual XTA drive replacement, even thought the XTIDE cards are an alternative?
                    I thought vwestlife made a important point in the linked video that XTA machines often have few or even no ISA slots. The early IBM PS/1 have no ISA slots and no XT-IDE type device. Tandy 1000 RL's only have 1 ISA slot. I think there are a few other machines with XTA connector but no ISA slots. Tandy 1100 maybe. I have a few projects I would like to work on and this one seemed most useful. A minimal sound blaster clone would be a lot of fun to develop also, but doesn't seem quite so useful. There are a bunch of sound card options, but there are zero XTA option as far as I know. Especially for the IBMs. Working Seagate 351 A/X's are not super uncommon, but working IBM drives for the Model 25, 30 or PS/1 don't seem to be very common.

                    There is a another point that is probably of less merit. You can get a little closer to the original experience with a solid state drive replacement. For sure, none of the glorious chirps that the WD steppers make. My XTA WD drive only works when it feels like it and when it does I am in early 90s heaven. One day it only worked once out of 20 boots, and when it finally did its thing, mmm-hm. This replacement would at least run the original bios. It is hard not to like all the color and options that XT-IDE offers but it does not feel period. I worked at a Tandy store (our Radio Shack) in the early 90's and I guess I have a desire to reproduce that to some level.

                    It is a weird thing that 30 year old electro-mechanical engineering is still far too advanced make reproductions of. I suppose that is a rabbit hole. Reproducing 60's silicon is bleeding edge amateur work right now.

                    I could have probably compressed all of that to: you can get solid state replacements for ATA, SCSI, MFM and floppy now, but not XTA. No ESDI either I suppose but I have no interest in that.

                    [EDIT]: I should probably note that at this point, it appears that IBM's 8 bit IDE used on the Model 25/30 and PS/1 is likely its own thing. I might have inadvertently signed up for two significant HD replacement projects.
                    Last edited by JayesonLS; September 9, 2021, 05:11 AM.

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                      #25
                      I ran my previous REPNZ OUTSB test on my Tandy 1000 TL/2 (8MHz 286). Scope capture below. The results are a little odd in that I never got a change on the IDE ~CS. Perhaps the TL/2 does not have it's XTA port at 320. Also, the time between ~IOW's is enormous compared to my 486 results. I expected it to be larger but this is crazy. I think I will just assume that the 286 timing is at least a bit longer than the 486 and move on.

                      NewFile1.png

                      Comment


                        #26
                        Originally posted by JayesonLS View Post

                        I thought vwestlife made a important point in the linked video that XTA machines often have few or even no ISA slots. The early IBM PS/1 have no ISA slots and no XT-IDE type device. Tandy 1000 RL's only have 1 ISA slot. I think there are a few other machines with XTA connector but no ISA slots. Tandy 1100 maybe. I have a few projects I would like to work on and this one seemed most useful. A minimal sound blaster clone would be a lot of fun to develop also, but doesn't seem quite so useful. There are a bunch of sound card options, but there are zero XTA option as far as I know. Especially for the IBMs. Working Seagate 351 A/X's are not super uncommon, but working IBM drives for the Model 25, 30 or PS/1 don't seem to be very common.

                        There is a another point that is probably of less merit. You can get a little closer to the original experience with a solid state drive replacement. For sure, none of the glorious chirps that the WD steppers make. My XTA WD drive only works when it feels like it and when it does I am in early 90s heaven. One day it only worked once out of 20 boots, and when it finally did its thing, mmm-hm. This replacement would at least run the original bios. It is hard not to like all the color and options that XT-IDE offers but it does not feel period. I worked at a Tandy store (our Radio Shack) in the early 90's and I guess I have a desire to reproduce that to some level.

                        It is a weird thing that 30 year old electro-mechanical engineering is still far too advanced make reproductions of. I suppose that is a rabbit hole. Reproducing 60's silicon is bleeding edge amateur work right now.

                        I could have probably compressed all of that to: you can get solid state replacements for ATA, SCSI, MFM and floppy now, but not XTA. No ESDI either I suppose but I have no interest in that.

                        [EDIT]: I should probably note that at this point, it appears that IBM's 8 bit IDE used on the Model 25/30 and PS/1 is likely its own thing. I might have inadvertently signed up for two significant HD replacement projects.
                        Thank you for the detailed explanation, it makes much more sense now.

                        Comment


                          #27
                          Originally posted by JayesonLS View Post
                          Anyway, the data point I was after is that there is 13 clocks between each ~IOW. I was hoping it would be just a little longer but it think it work for what I have in mind. My hardware plan was to use at ATMEGA328 at 20MHz with an external universal shift register to hold the data. And a GAL22v10 to provide some glue. I like this approach as the bill of materials is inexpensive, can be all through hole and anyone with a TL866 can program the chips. Plus the timings on these micros is quite predictable.

                          The idea is that on an IO write, the GAL would latch the data into the shift register and signal the ATMEGA there was data. The ATMEGA would then trigger an SPI read. The SPI read would take 8 10MHz bus clocks to get the data out of the shift register, leaving at most 5 10Mhz clocks / 10 20Mhz clocks for the ATMEGA to detect the signal from the GAL and trigger the SPI read. I think it will just work. Especially if there is a requirement to use lower bus clocks if someone, for some reason, wanted to use an XTA card in a fast PC.
                          Yay. I do know a *little* about the AVRs so maybe I could offer slightly more useful advice about those than ARMs.

                          Instead of using a shift register how about using a '573 parallel latch? If you use a contiguous port you can read a byte in a single instructions, access to the port registers is as fast as a memory read. The state machine you'll need to build into the GAL will be the same, IE, latch the data on a host WE signal and unlock it after the AVR signals a successful read. This will give you many more spare cycles to actually process the contents of a register write.

                          (FWIW, you might want to consider using the ATMEGA324 instead of the 328, because its larger number of I/O pins means it has several full 8-bit ports. From memory I think the '328 only has one? They cost about the same.)

                          Reads from the device feel like the trickier part to me:

                          2332_8088%20timing%20system.jpg
                          The device we're emulating doesn't have just one register, it has four, selected by A0/A1. On either a read OR write cycle we'll want to grab the contents of those two address lines immediately as CS is asserted; for writes you could save that in another external latch and get it for later, but for reads you'll want to immediately use it (it's valid at the end of T1) to select the correct data value the host is asking for so you'll have it on the bus in time for the end of T3. This definitely feels like an argument for doing parallel I/O instead of a shift register.

                          If you really wanted to throw hardware at the problem here's a terrible idea: There's an old part called the 74670 which is a 4 bit by 4 address dual-ported register. A value can be written in one side at any time and read back out anytime on the other. If you used four of these, two for input and two for output, you could create a hardware-speed external register set that you could read and write basically completely asynchronously and timing almost wouldn't matter as long as you updated them once every 4x cycles. Keep the GAL and use that as a status register/interrupt generator state machine for the AVR so you can signal to it when a host access has happened. And, well, you're also probably going to have to implement a state machine for DMA data transfers, but maybe that's getting ahead of ourselves.

                          (* Edit: Or instead of a pile of '670s another idea might be a dual-ported memory chip. Renesas makes several models, they're kind of expensive but they could do the same job and more. If you had a 1Kx8 chip you could use 512 bytes of it as an input/output buffer for DMA sector transfers and 8 bytes of what's left for the I/O registers...

                          Another nice part about using the memory chip or registers to completely isolate the AVR from the bus is you won't need an external tri-state buffer.)
                          Last edited by Eudimorphodon; September 9, 2021, 09:14 AM.
                          My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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                            #28
                            Originally posted by JayesonLS View Post
                            I ran my previous REPNZ OUTSB test on my Tandy 1000 TL/2 (8MHz 286). Scope capture below. The results are a little odd in that I never got a change on the IDE ~CS. Perhaps the TL/2 does not have it's XTA port at 320. Also, the time between ~IOW's is enormous compared to my 486 results. I expected it to be larger but this is crazy. I think I will just assume that the 286 timing is at least a bit longer than the 486 and move on
                            Did the TL/2 have a drive installed in it? According to this Tandy omnibus the 1000s with XTA ports do have them at 0x320. I wonder if the circuitry driving CS disables itself if it doesn't detect an XTA drive present. (Is that what the "ACTIVE" line on the bus is for? I can't find docs for that.) That would be a useful feature if a user installed a conventional HD controller instead.

                            As for the spaces between the IOW's, how is your test code generating the writes? This fastest way to transfer "arbitrary" data to I/O port on the 80186 and higher are the INS and OUTS instructions, which directly auto-increment from a starting address in RAM and push/fill RAM without the need of any LOOPs. A quick skim of the 286 reference manual says an OUTS takes 5 instruction cycles per REP, I'm not sure how that matches up with *bus* cycles on the 286 when it's doing 8-bit I/O with wait states, but in any case I think it's reasonable to expect that a 286 is likely to take "more" time than a 486. (The instruction timing counts in the 486 manual I simply have no idea how to interpret, but the 486 executes most non-I/O instructions *much* faster than the 286, which isn't even close to an instruction-per-clock for almost anything. And an XT is going to be even slower.) If you're just doing a series of non-string OUT without a loop, literally just directly transferring an already loaded register, then that probably would be the very fastest way to trigger IOW, but it's not exactly a "real world" case...

                            But, really, the timing that matters most is if I'm reading the 486 trace correctly you have 600ns between chip select and the end of the I/O cycle. If the plan is to fire an interrupt on CS the stated interrupt latency for the AVR appears to be 4 clock cycles after finishing whatever instruction is in flight. At 20mhz on the AVR that's going to be cutting it pretty close for reads, since you're going to have a minimum of 200ns latency and worst case... quite a lot if you were in the middle of something expensive and it has finish before responding to the int. If it could *always* just be 200ns you'd probably be okay since 400ns will give you 8 cycles to read A0/A1 to turn into an offset and read/write to see what the op is and read/assert accordingly, but the possibility that you could be neck-deep in something expensive when the interrupt fires complicates things.

                            This is where the harebrained idea of an external memory device to serve as the host-accessible read register might make sense. (Another idea for that is if the dual-port chip is too expensive you could make one yourself from a normal SRAM and some buffer/multiplexers since it strictly isn't necessary for it to be dual ported as long as you make sure you don't access it from the AVR during host cycles.)
                            My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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                              #29
                              Originally posted by Eudimorphodon View Post
                              This is where the harebrained idea of an external memory device to serve as the host-accessible read register might make sense. (Another idea for that is if the dual-port chip is too expensive you could make one yourself from a normal SRAM and some buffer/multiplexers since it strictly isn't necessary for it to be dual ported as long as you make sure you don't access it from the AVR during host cycles.)
                              Yet another option, albeit not necessarily a prettier one, would be to assign each of the four XTA registers to its own 8-bit output port of a sufficiently big C and to interface them to the bus using four 8-bit tri-state buffers.

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                                #30
                                I'm prototyping with the ST32F767 (100+ 5V tolerant I/Os) and the STM32F429 (same pinout). Is that enough?
                                Reach me: vcfblackhole _at_ protonmail dot com.

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