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8 bit IDE (XTA) Replacement Project

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    #31
    Originally posted by Benedikt View Post
    Yet another option, albeit not necessarily a prettier one, would be to assign each of the four XTA registers to its own 8-bit output port of a sufficiently big C and to interface them to the bus using four 8-bit tri-state buffers.
    It's a shame the '670 is kind of an abandoned part because a dual-port register like it is actually really useful. A bigger/wider one would be even better, but I guess at a certain point you're splitting hairs about whether it's just a dual-port RAM.

    The datasheet for the WD11C00-17, which is the bus interface portion of the WD1002 controller linked earlier, is interesting reading. FWIW, and this is oversimplifying a lot, it is a state machine that has roughly the equivalent of several 74670's built into it for the status registers, a read/write buffer, and control lines to run 1K's worth of static RAM used for sector buffers and caching ECC data and commands for the controller's processor. (The part where it appears to be smart enough to cache full multi-byte commands for the CPU is certainly interesting.) There's a block diagram on page 1-3 of the WD1002 manual that's kind of useful for visualizing the task at hand. My broad-stroke take on it is an AVR 8-bit CPU should be more than enough to do the job of the WD1015 and *parts* of the WD11C00-17 (you definitely don't need ECC generation anyway, and it's probably fine doing its own command serialization...). The SD card has no need for and otherwise does the job of the WD1010A disk controller and WD10C20 data separator components, so they're out . But because the AVR simply is not designed to be directly slaved to a bus (no built in tri-state or external port R/W direction control, nor a way to "DMA" based on an address input) the task would get a lot easier if you had help in the form of external memory buffering and a little clever state-machine-ing. It's all about latency. If the bus had a WAIT line on it you could pull with the GAL on every I/O operation then, yeah, don't need it, but lacking that makes external memory a *really* attractive workaround in my mind.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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      #32
      You may want to consider using a PIC32MX MCU (based on the MIPS R4000 architecture). In particular, have a look at section 13.4 here
      Reach me: vcfblackhole _at_ protonmail dot com.

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        #33
        Originally posted by Chuck(G) View Post
        You may want to consider using a PIC32MX MCU (based on the MIPS R4000 architecture). In particular, have a look at section 13.4 here
        ... the really juicy part seems to be section 13.4.3, "Addressable Buffered Parallel Slave Port Mode". In essence this mode looks like it's pretty much exactly what you'd get if you went with that idea of using four '670's and a state machine that'd let the processor know that a read or write happened. For some applications that it's limited to four addresses might be a bummer, but considering that's just what's needed here this actually might be the perfect solution.

        I've never programmed for PIC before but I'm really tempted to look into this because a project that's been gnawing on me is a floppy disk replacement that targets emulating the whole shebang at the controller level. It just so happens a Western Digital 177x-type controller has four registers as well...
        My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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          #34
          The PIC32 stuff isn't bad and the documentation isn't nearly as cryptic as the upper STM32F4 and F7 parts. If you want to program assembly, the instruction set is well-documented and not as involved as, say, ARM. The toolset is pretty good.

          I got my first whiff of it with the Digilent Uno32--board--basically a souped-up Arduino.

          I mostly use STM32 stuff now because it's more widespread, but the PIC32 isn't bad at all.
          Reach me: vcfblackhole _at_ protonmail dot com.

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            #35
            Originally posted by Chuck(G) View Post
            You may want to consider using a PIC32MX MCU (based on the MIPS R4000 architecture). In particular, have a look at section 13.4 here
            This was looking just perfect. All the needed registers in a 28 pin through hole device that costs about the same as an ATMEGA328. Things might get a little tight on pin count but I reckon it would work. Unfortunately it is a not a 5v device and while a few pins are 5v tolerant, most are not. At least not on the 28 pin part. Level shifting always seems like a pain in through hole designs. Maybe a couple of 74LVC245A's would do the trick. This might still be the way to go.

            A 5v micro with a single register and better than 80's performance would also be a good option. Only port 320 is full 8 bit IO register. From what I can gather, it reads/writes directly to the controller sector buffer SRAM and the SRAM address auto-increments. As long as the micro/register setup can keep up with the data coming in/out, all is good.

            For writes to the other 3 ports: Two just signal when they are written to (reset and request-start-of-command) and have no data. The last just has two bits to enable/disable DMA and IRQ. I think all of this would fit into the proposed GAL22V10.

            For reads from the other 3 ports: One is not used at all. One has 6 bits of status flags. One has 4 bits of drive size information. It should really only be 2 bits of drive info - the other 2 bits are for the second MFM drive which is impossible with XTA. A second drive in XTA presents as a second interface. However the two Seagate drives I have tested report their size info on both sets of bits. I suppose I should duplicate that behaviour just in case there is some BIOS somewhere that counts on it. These reads would not also fit into the one proposed GAL. I think an extra IC of some kind would be enough to take enough pressure off of the GAL. A register, tri-state buffer or maybe just a second GAL.

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              #36
              Originally posted by Eudimorphodon View Post

              Did the TL/2 have a drive installed in it? According to this Tandy omnibus the 1000s with XTA ports do have them at 0x320. I wonder if the circuitry driving CS disables itself if it doesn't detect an XTA drive present. (Is that what the "ACTIVE" line on the bus is for? I can't find docs for that.) That would be a useful feature if a user installed a conventional HD controller instead.
              There was something funny going on when I captured from the TL/2. None of the numbers make much sense so I am going to ignore the results until/unless I figure out what was going on. This test was using REPNZ OUTSB. I have a 1000 TX I can put the Seagate XTA card into and I'll see what I get there.

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                #37
                You can always go to the QFP packages. There are cheap adapters--I may even have few extra. Perfect for prototyping. A couple of years ago (well more, actually) I was working with the PIC32MX795 and still have a number of adapters unused (and am not likely to use). You populate them with a few capacitors and solder on the QFP and you're good to go. There's even a programming header for a PICKit programmer. Let me know.

                There's also the more recent PIC32MZ line--still has the master port and 5V tolerant I/O (can sink up to 32 ma per pin).

                Nowadays, it's STM32 for me, but that's mostly due to price and availability.
                Last edited by Chuck(G); September 9, 2021, 05:10 PM.
                Reach me: vcfblackhole _at_ protonmail dot com.

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                  #38
                  Originally posted by Eudimorphodon View Post
                  Instead of using a shift register how about using a '573 parallel latch?
                  That is definitely an option. The early Sound Blasters use something similar - a pair of 374's (one for each direction) and a 40 pin micro. I was looking for a bidirectional register to reduce chip count and could not find one. I did come across at least one suitable shift register though and that would make it easier to use a micro with less pins. I thought the FreHD for the Tandy Model 3/4 was doing something like this, but it is not - it uses a one-way shift register for reads. For writes and read setup time, it halts the Model 3/4 CPU.

                  Originally posted by Eudimorphodon View Post
                  (FWIW, you might want to consider using the ATMEGA324 instead of the 328, because its larger number of I/O pins means it has several full 8-bit ports. From memory I think the '328 only has one? They cost about the same.)
                  This does seem like a great option for a 5v, 40 pin micro. It is a little more costly than a 328, but not much so.

                  Originally posted by Eudimorphodon View Post
                  If you really wanted to throw hardware at the problem here's a terrible idea: There's an old part called the 74670 which is a 4 bit by 4 address dual-ported register.
                  I have a sleeve of these - I was thinking of designing a DMA circuit for old Tandy's.

                  I think for this project, if we are adding that much external memory, it is time to bite the bullet and use a CPLD.

                  Originally posted by Eudimorphodon View Post
                  And, well, you're also probably going to have to implement a state machine for DMA data transfers, but maybe that's getting ahead of ourselves.
                  Yeah, there are a lot of parts to implement.

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                    #39
                    The problem with CPLDs on old-school hardware is that there are very few 5V CPLDs--there are some with 5V tolerant inputs, but the only true 5V one that I know of is the Atmel ATF1504AS, but I don't know if Microchip is just shipping old stock.

                    Gone are the days of my favorites the Xilinx XC95 devices in PLCC fully 5V compatible.
                    Reach me: vcfblackhole _at_ protonmail dot com.

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                      #40
                      Originally posted by Chuck(G) View Post
                      The problem with CPLDs on old-school hardware is that there are very few 5V CPLDs--there are some with 5V tolerant inputs, but the only true 5V one that I know of is the Atmel ATF1504AS, but I don't know if Microchip is just shipping old stock.

                      Gone are the days of my favorites the Xilinx XC95 devices in PLCC fully 5V compatible.
                      Yeah. If PLCC XC9572 was still a thing, I would probably just drop one of those and an AVR on a board and move on. You can still source them - they are used in the CocoSDC. I think Ed Snider gets them from UTSource. Who knows for how long though.

                      I guess the ATF150x might not be a bad choice. And if it disappears, then switch the design to a pile of GALs. And if Microchip stops making those, used GALs are currently plentiful. I think the more general problem is that any 5v through hole friendly part has some risk of disappearing.

                      Actually, a board with an ATF1508 and a micro might be just the thing for development. Then optimize part selection later. I am not sure at all right now how to wire everything up and I am not a big fan of soldering a lot of wires during prototyping. The only thing giving me pause is imagining all the wincupl bugs I might run into. I am not clear on how to program it either.

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                        #41
                        Originally posted by JayesonLS View Post
                        I thought the FreHD for the Tandy Model 3/4 was doing something like this, but it is not - it uses a one-way shift register for reads. For writes and read setup time, it halts the Model 3/4 CPU.
                        I suspected they probably did, the TRS-80 bus has a pretty easy to use WAIT line. Not having that facility on this bus is going to make this pretty tight on any MCU that doesn't specifically have a get-out-of-jail-free card like that input port on the PIC32.

                        (I am still very curious about that PIC's latency for reacting to the "this port was touched" events. On most machines likely to actually benefit from an XTA hard disk replacement if you can react to a value being read or written and update the register in something around the 1-microsecond ballpark that's probably enough?)

                        This does seem like a great option for a 5v, 40 pin micro. It is a little more costly than a 328, but not much so.
                        My big AVR project (currently on hold because of real life) started with a 328 and a GAL programmed to be an autoincrement counter for the LSB of a video address but going to the 324 and just using two ports for the MSB/LSB made life so much easier and more flexible. (I can do arbitrary strides through memory just by changing the increments, etc.)

                        I have a sleeve of these - I was thinking of designing a DMA circuit for old Tandy's.

                        I think for this project, if we are adding that much external memory, it is time to bite the bullet and use a CPLD.
                        As Chuck notes if you don't want voltage shifters there's not much in CPLD-land these days. A 74LVC245 might be *fine* even running bidirectionally because the PC bus should react to TTL level output highs, which are spec'ed at only 2.7 volts. Assuming it runs close to the rails like most CMOS devices I would think it should drive the bus adequately with a 3.3v VCC? You'll need 3.3v anyway for the SD card, so if the PIC will do the job it seems like a really attractive option.


                        Yeah, there are a lot of parts to implement.
                        I am *not* at all familiar with how fast DMA cycles are on the ISA bus compared to the 8088 cycles (I assume they replicate the T-state counts similarly), but assuming they *mostly* look like normal reads and writes in terms of latency and you can put together a bus interface that can respond to those with adequate latency then maybe the DMA isn't going to be that big of a deal? You'll need some flip-flop logic to assert DRQ and accept a DACK as the signal for the next byte to be supplied/processed, and at the end of the transfer (presumably in a case where you've transferred a full 512 byte sector?) you'll need to fire the interrupt pin. I don't know if that PIC32 will be able to handle that just through GPIO, but it is pretty fast in theory and if instead of using interrupts you switch to a tight polling loop during DMA transfers I'd think this might be surprisingly doable.
                        My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

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                          #42
                          I did some testing on 8 bit ISA (8237 type, not bus-mastering) DMA some years ago and found, much to my disappointment that maintaining a 1MB/second rate was pretty much the limit. 16 bit 0WS should double that.
                          Reach me: vcfblackhole _at_ protonmail dot com.

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                            #43
                            Originally posted by Eudimorphodon View Post
                            Is that what the "ACTIVE" line on the bus is for? I can't find docs for that.) That would be a useful feature if a user installed a conventional HD controller instead.
                            The signal on pin 39 next to ~CS? That is the drive active signal for the activity LED.

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                              #44
                              Originally posted by Chuck(G) View Post
                              I did some testing on 8 bit ISA (8237 type, not bus-mastering) DMA some years ago and found, much to my disappointment that maintaining a 1MB/second rate was pretty much the limit. 16 bit 0WS should double that.
                              I am not super fussed about performance given that the original drives are not all that fast.

                              I do think I need to do some more testing with different interfaces and machines to figure out worst case timings. I am only getting about 100k/s from my ST351 A/X in my 486 board. I just watched VWestlife's video again and he is getting more than double that in a 286 Tandy.

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                                #45
                                Originally posted by Eudimorphodon View Post
                                You'll need 3.3v anyway for the SD card, so if the PIC will do the job it seems like a really attractive option.
                                I was going to use one of the (micro)SD to pin header adapters available on eBay, Ali, etc. for very little money. They include a 3.3v regulator and level shifting to 5v. The full size SD modules do export 3.3v on a pin - might be enough to run the micro.

                                What environment do you use to program your AVRs?

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