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8 bit IDE (XTA) Replacement Project

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  • JayesonLS
    replied
    The programmable IO program for control register reads is now implemented. Port 321 and 322 are returning expected values. 320 and 324 are not responding as expected. This is with my 486 ISA bus overclocked to 16MHz and the timings seem to be (just) good enough.

    IMG_20211121_200609909.jpg

    I have to say, while using the programmable IO on the Pico is super interesting, I am not sure I would recommend others follow. Hard, low-level programming is my day job and I am finding this slow going and quite challenging. I think it would have been much easier for me to use programmable logic, and say, a STM32. And I am just a tinkerer with programmable logic. With PIO, you just need 10 or 20 crazy tricks and after that it is smooth sailing.

    The control register read program has all sorts of tricks going on. Complicated branching and fall-throughs. Pins in just the right order so I can use decrements for decoding, or so bits are in just the right spot when needed to shift into another register. Look at this program flow I annotated for it:

    Annotated Program.png

    And there is a second program that watches for when this one flips the transceiver direction.

    Leave a comment:


  • Theoryboy
    replied
    This is facinating, following with great interest. Might be useful on the Schneider EuroPC

    Leave a comment:


  • JayesonLS
    replied
    Some more baby steps forward. I was hoping to be a bit further forward at this point but progress is progress. I have implemented the handling of control register writes via the Pico's programmable IO.

    This hardware connected to an XTA interface card:

    IMG_20211119_130313735.jpg

    plus these commands on the DOS PC:

    IMG_20211119_130352020.jpg

    gives this debug output over the Pico's USB cable:

    IMG_20211119_130450474.jpg

    Optimizing Pico programmable IO programs is very dependent on pin ordering, hence the big old mess of wires.

    Leave a comment:


  • JayesonLS
    replied
    So this is fun! My first prototype boards for the XTA replacement came in. Because the RPi Pico IO is so programmable, I was able write something that captures reads and writes going through the IDE cable. I did some capture of the boot sequence communications that happen with different drives against different BIOSes.

    IMG_20211112_092510578.jpg XTA LA Captures Sheet.PNG

    I've learnt a lot already. The reset register does a very light reset - just cancels any previous command I think. The BIOSes expect the hardware to respond immediately after resetting this way. The Seagate BIOS resets between every command. The WD BIOS constantly spams the select register - I had assumed this register was a write-once-and-wait setup, but WD does not expect it to work this way. The Seagate BIOS use DMA for transferring sector data but not IRQ. An interesting data point is that the drive only DMA's the 512 bytes of sector data, then returns the final operation status byte via a normal IO read from the data register. The WD BIOS enables IRQ for all operations, even commands that retrieve only 1 byte. It is almost like implementing two different interfaces.

    My one working drive, a ST351A/X, has very tight bearings after running for a couple of hours. It stopped spinning so fast on power off that I am worried it may not spin up again. Definitely needs to be used sparingly going forward.

    My non-working ST325X does actually read the first sector during boot without error. However the low level format fails after a valiant effort and fdisk claims there is no fixed disk at all. One working sector will be good enough to measure DMA timing if the 351 doesn't make the distance. [EDIT]: Seems that the low level format I did a while back did help the drive some. fdisk does detect the drive now and will partition it after a large number of reseeks. Unfortunately format gives up fairly quickly. The poor thing has been treated badly - all banged up - even one of the rubber shock mounts has been torn off. Actually quite good enough for my needs though.

    My WD drive never reports ready for a command, so definitely no good I think. I can't help but wonder if it is repairable. The last time it did work, it happened on a ctrl-alt-delete after many previously failed boot attempts. Nothing much happens on a warm boot other than the register reset command and waiting for the drive to be ready to take a command.
    Last edited by JayesonLS; November 12, 2021, 05:20 AM.

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  • JayesonLS
    replied
    I'm not sure how interested folks are in the implementation details but figure I might as well post them in case someone is.

    While I wait for boards to come in I have been experimenting with the Raspberry Pi Pico programmable IO. I wrote a couple of logic analyzer type programs to capture what is happening on the bus when the PC is communicating with a real drive. This will run on a slightly modified version of the drive hardware which already has needed signals on the cable connector. One program samples all signals on the bus at high speed and keeps a timestamp. It also filters out any duplicate frames so the Pico memory is not exhausted too quickly. This is for gathering things like precise timing of DMA and IRQ signals. The Pico easily overclocks 2x to 250MHz which gives a 35MHz sampling rate. The other program just makes one capture per read/write so I can capture all of the communications between the PC and drives. This should let me see the communication sequences on my one working drive and I am also interested to see what my two non-working drives do as well.

    I have also been doodling with the PIO programs for the actual drive firmware. Mostly just to feel out how they will be implemented and what the final pin connections to the Pico will be. I am pretty sure at this point that I was quite wrong with my earlier statement that a Sound Blaster Pro might be possible with no glue logic. I think an original Sound Blaster would probably be possible with some glue logic. While the PIO is quite flexible and probably Turing complete, the limited instruction set does mean programs tend to be long. I am confident about implementing the 8 bit drives without any additional glue logic however it did take a while to find an approach that will work. Large programs that implement multiple things at the same time use less total instructions however run too slow. Programs that implement single pieces of functionality (like writing to one register) run faster but use more instructions in total. The entire budget on the Pico for PIO is only 64 instructions which is fairly tight. I got kind of lucky that the data register can not be written and read to at the same time, nor even accessed unless the drive indicates it is not busy. This will let me swap between IO read, IO write, IO read DMA and IO write DMA programs for that register. If all of those had to work at the same time I would be in a tough spot.

    Here is a particularly tricky (untested) example which handles reads from the drive's status register. It is a bit special in that it merges in current IRQ and DRQ pin state with other state bits. The only other palatable way I can think of to implement this would be to use programmable logic.

    Code:
    ;-----------------------------------------------------------------------------------------
    ; Register 1 is the flags register.
    ;
    ; Note: We must constantly pull from the FIFO to keep the
    ; register value up to date.
    ;
    ; 13 instructions.
    ; Up to 13 cycle delay to set up data (+ ~4 cycles in external delays)
    ; Allowed total delay ~27 cycles with 125MHz Pico & 10MHz ISA bus
    ;-----------------------------------------------------------------------------------------
    .program read_register_1
    .side_set 1 opt                     ; Side set maps to data_dir
    wait_for_read_start:
        pull noblock                    ; Keep read values up to date. If FIFO is empty,
        mov x, osr                      ; X is moved to OSR. So save read values in X.
        ; For 1 cycle lower worst case latency we can do a "jmp pin wait_for_read_start" here on ~IOR.
        mov osr, pins                   ; in pins are configured to start at ~IOR
        out y, 4                        ; Shift ~IOR, ~CS, AEN and A1 into Y (want all 0)
        jmp y-- wait_for_read_start
        out y, 1                        ; Shift A0 into Y (want 1)
        jmp !y wait_for_read_start      ; Jump if A0 not 1
       
    do_read:
        in osr, 2                       ; Shift in DRQ and IRQ still sitting in OSR
        in x, 4 side 1                  ; Shift in the 4 status bits from X and side set tranceiver direction
        mov osr, isr                    ; (Setting tranceiver direction will result in set_pindirs setting pindirs)
        out pins, 8                     ; Set data.
        wait 1 pin 9                    ; Wait for ~IOR high
        irq 3 nowait                    ; Signal to restore pindirs and tranceiver direction.
    
    ;-----------------------------------------------------------------------------------------
    ; Waits for data_dir to go high and then sets pindirs accordingly.
    ; Waits for interrupt signal before restoring.
    ;
    ; in and out pin mappings should be 1 bit starting at data_dir
    ; set pindir mapping should be 5 bits starting at D0
    ; side set mapping should be 3 bits starting at D5
    ;-----------------------------------------------------------------------------------------
    .program set_pindirs
    .side_set 3 opt pindirs             ; The 3 bits are pindirs for D6-D8
        wait 1 pin 0                    ; Wait on data_dir to go high (pin 22)
        set pindirs, 31 side 7          ; Pindirs set to out for all 8 data bits. 74LVC245 transceiver should have reversed by now.
        wait 1 irq 3                    ; Wait for signal to reverse pindirs / tranceiver direction
        set pindirs, 0 side 0           ; Restore all pindirs.
        mov pins, null                  ; Restore data_dir (tranceiver direction). Must not be before pindirs.
                                        ; Could be at same time however but would require using pindir / pull down to effect this.
                                        ; An option if we end up being an instruction over budget.
    Optimization of these is challenging and I am always seeing improvements. I have juggled pin assignments numerous times to combine or remove operations. When I pasted this code in initially, read_register_1 was 18 instructions with 18 cycles of read setup time. This was getting close to my calculated maximum of 23 cycles of setup time. Before hitting send I saw improvements and some time later I had it down to 14 instructions and 14 cycles of latency. Then I decided to do this goofy thing to have another program change the Pico pin directions when it sees the bus tranceiver direction change. It increases the overall size of PIO programs by two instructions but reduces latency on all reads by 1 cycle. So now it is down to 13 cycles of read setup time which leaves a large margin of error.

    I was not able to implement the functionality where writing to the select register immediately sets busy flags in the status register. Implementing register reads and writes in one program was leading to high instruction counts and high latencies. I also did not have a spare register to efficiently hold the latched busy state. So instead I will dedicate the second CPU core to run a tight polling loop to manage the status flags. I have at least 50 CPU cycles from when the PIO signals the select register to when the status register value needs to be set (time between x86 OUT and following IN instruction). This should be plenty. I would be sweating things a bit on a single CPU micro. The main CPU will have a bunch of other interrupts firing. While none of these interrupts will be particularly time sensitive they could make it tricky to implement a tight polling loop or very fast interrupt handler.

    Leave a comment:


  • vwestlife
    replied
    Originally posted by Svenska View Post
    Either the last head contains diagnostic (or factory) data, or they use a more efficient encoding internally (RLL instead of MFM) and allocate the additional space as an additional head to avoid changing the geometry.
    The Western Digital 20, 30, and 40 MB IDE-XT drives all have physical parameters of 782 cylinders and 27 sectors per track. The only difference is 2, 3, or 4 heads.

    Leave a comment:


  • Svenska
    replied
    Originally posted by JayesonLS View Post
    The original PCDOS 2.0 for the 5160 does come with fdisk and creates an MBR. It only allows creation of one partition - apparently you were supposed to create more partitions for other operating systems. Although how exactly is not clear to me.
    Microsoft XENIX comes with its own FDISK utility, and so does OS/2. DOS simply ignores foreign partitions, and FDISK cannot not create such partitions because it does not know if other restrictions apply. (Although DOS FDISK shows XENIX partitions by name.)

    While partitions should generally start and end on a cylinder boundary, it is not a strict requirement. But I think some versions of DOS (or other operating systems) require it for their partitions, at least. Some boot managers also require the remainder of the first cylinder to hide (e.g. GRUB), but others use their own partition (e.g. OS/2) or are made small enough (XFDisk).

    Originally posted by vwestlife View Post
    The 20 MB drives have one platter (two heads) and the 40 MB drives have two (four heads). But I dunno about the WD 30 MB drives -- they're listed as having 3 heads. So maybe they're actually 40 MB drives with one faulty platter surface? An easy way to make use of parts that otherwise would be discarded
    Either the last head contains diagnostic (or factory) data, or they use a more efficient encoding internally (RLL instead of MFM) and allocate the additional space as an additional head to avoid changing the geometry.

    Originally posted by Eudimorphodon View Post
    That doesn't quite make sense to me given I *thought* the only place geometry is supposedly mentioned in the MBR is in the individual partition entries, but... shrug. I didn't dissect the MBR to see if DOS had created some dummy "free space" entry in another slot or anything.
    Unfortunately, some parts of the drive geometry are part of the FAT BPB, and some versions of DOS will corrupt other partitions if they don't match the drive. The 8 GB limit only applies to the maximum 1024/255/63 CHS values; if the BIOS assumes 17 sectors/track instead of 63, you end up with a 2.1 GB limit instead. The ECHS translation does not change the sector count (it keeps doubling heads/halving cylinders).

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by vwestlife View Post
    None of the 40 MB IDE-XT drives are "wasting a head". They're simply using the 980/5/17 parameters because those were the most common, based on Seagate's ST-251.
    ... Yeah, I forgot about that reason for translation. Many early IDE drives used translation specifically to emulate drive geometries that were common in AT BIOS drive type tables. Having a user-specified type wasn't really common until 1990 or so.

    I guess I will note that I have discovered it may be possible to confuse FDISK if you image a disk to the "wrong" size so maybe we can't entirely rule that out. I was experimenting at one point with using an emulator to get PC-DOS 7 installed directly off a CD-ROM distribution of it to use on my Tandy with XTIDE, and while that "worked" to generate a 2GB image and DD-it onto the flash device subsequently I discovered that I couldn't use FDISK on the Tandy to make any additional partitions. Normally you should be able to use the first 8GB of a drive (max supported by DOS CHS translation), but for some reason the 2GB total size from the DD'ed emulator image was "honored". That doesn't quite make sense to me given I *thought* the only place geometry is supposedly mentioned in the MBR is in the individual partition entries, but... shrug. I didn't dissect the MBR to see if DOS had created some dummy "free space" entry in another slot or anything.

    Leave a comment:


  • vwestlife
    replied
    None of the 40 MB IDE-XT drives are "wasting a head". They're simply using the 980/5/17 parameters because those were the most common, based on Seagate's ST-251.

    The 20 MB drives have one platter (two heads) and the 40 MB drives have two (four heads). But I dunno about the WD 30 MB drives -- they're listed as having 3 heads. So maybe they're actually 40 MB drives with one faulty platter surface? An easy way to make use of parts that otherwise would be discarded.

    Leave a comment:


  • JayesonLS
    replied
    Originally posted by Eudimorphodon View Post

    Long story short, unless you’ve cracked open the actual physical drive and counted platters assume all BIOS geometries listed for a given XTA hard disk technically are lies. Pure unadulterated BS.
    I didn't mean to refer to physical heads. I should not have confused things by referring to platters. All I know is that it had a 20-something meg partition on a 40 meg drive and fdisk seemed to think it was full. Maybe it just got imaged that way at the factory. I am hoping that one day it will come alive again. It had a few bad sectors which I was quite happy about so I could see how the drive behaved on read errors.

    Leave a comment:


  • Eudimorphodon
    replied
    … FWIW, though, some real hard drives had an odd number of data heads. Early voice coil positioner drives often used a “dedicated servo” surface on one platter, meaning one head was used solely to read information written when the drive was manufactured to provide positioning feedback, Most modern drives use “embedded servo” info instead, where data shares the same surface.

    This is why you can destroy modern hard drives irreparably by running them through a bulk eraser. Erase the servo info and the drive is boned, you can’t write it back with the voice coil.

    Leave a comment:


  • Eudimorphodon
    replied
    Re: your suspicions that the Tandy TL/2 was “wasting a platter” on a drive, that’s highly unlikely.

    One thing you’ll notice when you look at the specs for these XTA drives is the very same drive model will list multiple possibilities for the geometry. This is *not* because they made a bunch of secretly different versions of the hardware, it’s because many (most?) of these drives used translation schemes to camouflage their true hardware configuration. Some of these drives that claimed to have up to six heads in the BIOS had as little as two (a single platter) in real life. (ST351/AX) This Statson reference for some Western Digital XTA drives has a couple tables in it showing different virtual geometries for the same 40 MB drive:

    https://stason.org/TULARC/pc/hard-dr...HH-IDE-XT.html

    If set to fake 17 sector tracks it had “five heads”, if set for 27 sectors it had four.

    I know it sounds stupid today, but in the late 80’s there was all kinds of ridiculousness going on with hard disks. Some low level optimization/data recovery tools made catastrophically stupid assumptions, like that all hard disks had 17 sectors per track, and it was enough of a problem that some manufacturers thought they needed translation to hide that. And hard disks also started being made with more than 1024 tracks, which the standard INT13h/DOS CHS format didn’t support, so you needed translation for that. And really high capacity hard disks were starting to use zone density recording to fit more data on the longer outer tracks of the disk, which completely blows up CHS entirely, so you need translation for *that*…

    Long story short, unless you’ve cracked open the actual physical drive and counted platters assume all BIOS geometries listed for a given XTA hard disk technically are lies. Pure unadulterated BS.

    Leave a comment:


  • JayesonLS
    replied
    Originally posted by 1ST1 View Post
    Will it be configureable? I mean, that I can set up a specific XTA harddisk type from specific manufacturer like 20 MB Conner, or can I tell the CHS data for the drive image on the SD-Card? Another sexy thing would be that I can swap between different diskimages with a button (or by software) ? I know during that there should not be a disk access and then the system needs a reboot. And one more neat function for at least FAT partitions would be if the device can extract the files inside the image to a separate folder on the SD card so that it is easy for file transfer. Maybe also the other way arround to get data into the disk image...
    CHS Parameters

    The drive, will for sure, always work with any CHS parameters the system BIOS is using. It can do this because I will make the minimum primary SD card size 128MB. [EDIT: I am not sure it is even possible to buy MicroSD cards under 128MB]. Any CHS parameter mismatch between the BIOS and drive just means sectors will not be written in contiguous order. Or in other words, there will be unused sectors sprinkled across the SD card. Sectors not being contiguous means the file system on the SD card would not be accessible if used in a modern PC.

    Most of the recent thread discussion has been how to configure the drive with CHS parameters so the sectors end up on the SD card in contiguous order. Eudimorphodon came up with a couple of great approaches on how to do this automatically. Assuming sufficient time and motivation, I am open to implementing versions of those and also a fully explicit CHS configuration. In the end, I am not overly concerned about the primary SD card being usable in another PC. I think it is most useful for getting files back and forward, especially when setting things up the first time. The plans for the secondary SD card will offer a couple of alternate ways of doing that. I am most keen on the ability to mount a floppy disk image as the A: drive. Making 360K or 720K floppies tends to be quite involved and error prone. A lot of the target machines seem to have unreliable floppy drives also.

    There are challenges with trying to match specific drive parameters. All drives I have looked at have jumpers and the Seagate ST351 A/X for example has more configurations than I think I will ever figure out. Even if the drive is configured to match a real drive, there is still no guarantee that the BIOS CHS values match. They don't in the case of an early Commodore CPx0 BIOS I read about yesterday. It interprets 40MB drives as 10MB. I also suspect my Tandy TL/2 was wasting a head (entire platter surface) on the WD drive it came with. The drive seems to longer be working so I can't confirm that now. The better approach seems to be tell the drive what the BIOS is using. Or just not bother and skip being able to read the primary SD card in another PC.

    All that said, it does makes sense for a 2.5" version of the drive to default to the CHS parameters for the little Connor 20MB.

    Where I use the term CHS above, I really only care about heads and cylinders. The drive will always handle cylinder values up to the max possible (1023 or 1024, I can't recall what the max is).

    Hard Drive Images

    I think if I support booting hard drive images, it will be a bonus, advanced feature and the images will live on the secondary SD card. I know it would be quite powerful and seems especially useful because you could create the drive image in an emulator. Things can get very fussy about CHS values matching and the failures are hard to diagnose - usually the system crashes trying to boot DOS. I think even the cylinder count being a little off can cause problems and the vintage PC BIOSes sometimes have slightly lower cylinder counts than the physical drives.

    Leave a comment:


  • Eudimorphodon
    replied
    Originally posted by JayesonLS View Post
    You are correct from what I can tell. The original PCDOS 2.0 for the 5160 does come with fdisk and creates an MBR. It only allows creation of one partition - apparently you were supposed to create more partitions for other operating systems. Although how exactly is not clear to me.
    Microsoft just kicked that ball over the fence, assuming that any alternative OS would come with an FDISK/installer smarter than theirs and just giving you the option to leave empty space for that other, smarter FDISK was where their responsibility ended.

    Complicating MBR sniffing slightly, PCDOS 2.0 fdisk creates the DOS partition in the fourth partition slot, leaving the first three slots blank. The DOS partition also starts on the second sector. DOS 3.3 or 6.22 (I can't remember which) on the other hand started the first partition on an even sector boundary (first track, second head, first sector).
    It's only the end positions you care about, so if you go with the MBR analysis strategy just assume you should check all slots. Since the "must end on cylinder boundaries" thing seems like a pretty safe assumption reading *any* populated partition entry should give you the highest head and sector numbers, which is strictly all you care about. (As noted, doesn't matter if the drive thinks it has 1024 cylinders but the BIOS thinks it's only 900 or whatever, doesn't affect the CHS to LBA translation.

    I guess it is also worth noting that strictly speaking the physical order of partitions in the MBR doesn't need to correspond with their position on the disk. It is technically valid to have the partition in the lowest cylinders in the highest MBR slot and vice-versa. It's probably bad practice, sure, but it is *allowed*.)

    This is, again, strictly speaking, the advantage of my suggestion of running some kind of program that directly just makes an INT13h call and instructs the drive to read the last sector, whether you do it the fancy fake MBR way or, for Rev 0, just run this binary off a floppy. It eliminates all possible ambiguity. (If you look up some of the ugly details about, say, partition type labels, there does exist the possibility that, say, if you expect a DOS partition entry to be a particular type there may be some OEM version of DOS that used something else.)

    FWIW, I would say that DOS 2.x is going to be a pretty rare edge case. It was *long* obsolete before XTA hard drives came out. The oldest machines I can think of with XTA ports are, what, 1988-ish vintage? About the only computer still on the market still shipping with DOS 2.x that late was the little stub inside of a Tandy 1000HX's ROM, and that version of DOS didn't even come with FDISK on the utility disk.
    Last edited by Eudimorphodon; October 25, 2021, 10:57 AM.

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  • 1ST1
    replied
    Will it be configureable? I mean, that I can set up a specific XTA harddisk type from specific manufacturer like 20 MB Conner, or can I tell the CHS data for the drive image on the SD-Card? Another sexy thing would be that I can swap between different diskimages with a button (or by software) ? I know during that there should not be a disk access and then the system needs a reboot. And one more neat function for at least FAT partitions would be if the device can extract the files inside the image to a separate folder on the SD card so that it is easy for file transfer. Maybe also the other way arround to get data into the disk image...

    Leave a comment:

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