Purpose of U90 in XT second revision board

[reenigne]

I've heard before that the first revision of the XT system board was missing U90 but I never knew what that IC actually did. After it was mentioned in another thread I decided to try to figure out what it did. I found the updated schematic in the March 1986 technical reference, and the difference seems to be this:

In the first revision, input D3 to U88 is -S0 AND -S1 AND -LOCK AND HRQDMA. In the second revision, this is changed to (-S0 AND -S1 AND -LOCK AND HRQDMA) OR (NOT (-DMACS' OR -XIOW')) (U90 is 2-input OR gates, probably a 74LS32). In other words, this input is forced high when writing to the DMA controller registers (IO ports 0x00-0x1f: the 8237). The output Q3 from U88 goes through a couple more flip-flops to HOLDA (the hold acknowledge input to the 8237). There might be some slight timing differences visible to software due to this change, but it would only be when writing to these registers if at all.

So what I think this is is some logic to fix a race condition between the CPU and the DMA controller. I suspect there was a rare situation where the CPU writes something to the DMA controller at the same time that a DMA access happens, the CPU and the DMA controller end up waiting for each other and the system locks up completely. That's just a guess though.

The other major difference seems to be the removal of the TD2 7ns delay line which delays the clock input to the 8237. I wonder if this was an earlier (and not completely reliable) method of solving the same problem. I don't think this difference would be visible to software since 7ns is so much shorter than a clock cycle, but I suppose it could be if it causes DMA accesses to happen a cycle later.

If anyone else has any more concrete information about these changes, I'd be fascinated to hear it.

 

[Chuck(G)]

From a historical perspective, that--a race condition--would be my guess also. A 7nsec. delay line on LSTTL is ridiculous--and expensive. Consider that the spec sheet for a 74LS00 puts the propagation time between 3 and 10 nsec, for example.

Have you compared this with the 2nd edition 5150 board?

 

[reenigne]

I just looked at the April 1984 5150 TR and that still has the delay line and no U90 equivalent - maybe there was no spare spot on the 5150 board to put another IC without a major redesign.

 

[Great Hierophant]

There is no U90 on my 256-640K XT system board. It only goes up to U89.

 

[per]

There is no U90 on my 256-640K XT system board. It only goes up to U89.

On the first revision boards the space for U90 was just labbeled "Spare". Most of the remaining boards were patched at the end of 1983/early 1984, before they changed the PCB layout.

The change occured at about the same time as submodel 087 of the XT was substituted with submodel 086. I wonder if that's a coincidence :roll: .

 

[sergey]

In the first revision, input D3 to U88 is -S0 AND -S1 AND -LOCK AND HRQDMA. In the second revision, this is changed to (-S0 AND -S1 AND -LOCK AND HRQDMA) OR (NOT (-DMACS' OR -XIOW')) (U90 is 2-input OR gates, probably a 74LS32).

So what I think this is is some logic to fix a race condition between the CPU and the DMA controller. I suspect there was a rare situation where the CPU writes something to the DMA controller at the same time that a DMA access happens, the CPU and the DMA controller end up waiting for each other and the system locks up completely. That's just a guess though.

The other major difference seems to be the removal of the TD2 7ns delay line which delays the clock input to the 8237.

Please forgive me for reviving an old thread...

You're right about the purpose of U90 - It is there to prevent a race condition where CPU is writing to the DMA controller while DMA controller is trying to initiate a DMA transfer. This logic (-S0 AND -S1 AND -LOCK AND HRQDMA) finds passive CPU cycles when DMA transfer is requested, puts CPU in wait mode and activates the DMA controller (using HOLDA signal).

Regarding the circuit with TD2 delay line. This circuit adjusts DMA clock duty cycle. The 8088 CPU needs clock with 33% duty cycle (and such clock signal is generated by the 8284 clock generator), but the 8237 DMA controller requires clock with a duty cycle more close to 50% ( >70 ns high / >50 ns low to be exact), so the solution is to pass the clock signal through some logic (74LS244 in XT's case) or/and a delay line and then do a logical OR with the original clock signal. It looks like 74LS244 alone extends the "high" phase enough (from 69 ns to 81 ns), but it is possible that in older XT they were using older variants of 8237 (e.g. AMD Am9517A) that required even longer "high" phase, and so additional delay line was added. By the way Taiwanese XT clones simply employed four 74LS04 gates connected in series.

 

[reenigne]

You're right about the purpose of U90 - It is there to prevent a race condition where CPU is writing to the DMA controller while DMA controller is trying to initiate a DMA transfer. This logic (-S0 AND -S1 AND -LOCK AND HRQDMA) finds passive CPU cycles when DMA transfer is requested, puts CPU in wait mode and activates the DMA controller (using HOLDA signal).

Good to know - thanks! I'm curious whether this would lead to a software-detectable difference between board revisions. I guess the lockup doesn't happen every time the DMAC is accessed during a DMA transfer or the machine would hang in something like 1 in 18 floppy drive accesses due to the DRAM refresh DMAs. So presumably some "harmless" DMAs will also get delayed by a bus cycle when they happen at the same time as a DMAC transfer.

Regarding the circuit with TD2 delay line. This circuit adjusts DMA clock duty cycle. The 8088 CPU needs clock with 33% duty cycle (and such clock signal is generated by the 8284 clock generator), but the 8237 DMA controller requires clock with a duty cycle more close to 50% ( >70 ns high / >50 ns low to be exact), so the solution is to pass the clock signal through some logic (74LS244 in XT's case) or/and a delay line and then do a logical OR with the original clock signal. It looks like 74LS244 alone extends the "high" phase enough (from 69 ns to 81 ns), but it is possible that in older XT they were using older variants of 8237 (e.g. AMD Am9517A) that required even longer "high" phase, and so additional delay line was added. By the way Taiwanese XT clones simply employed four 74LS04 gates connected in series.

Fascinating stuff - thanks again!

 

[pearce_jj]

One thing I did notice in testing DMA on an '84 board is that DMA transfers would sometimes fail where multiple DMA operations were ongoing concurrently. Specifically, running an SB-Pro at 22kHz with DMA disk transfers (both demand mode), one of the DRQs raised by the disk controller would apparently be missed, which I worked around by checking the DMA transfer complete bit when the end had apparently been reached. This never happened unless the SB-Pro was running.

That said this was early in my development so it may well have been poor logic on the disk controller too.