reenigne
Veteran Member
I've heard before that the first revision of the XT system board was missing U90 but I never knew what that IC actually did. After it was mentioned in another thread I decided to try to figure out what it did. I found the updated schematic in the March 1986 technical reference, and the difference seems to be this:
In the first revision, input D3 to U88 is -S0 AND -S1 AND -LOCK AND HRQDMA. In the second revision, this is changed to (-S0 AND -S1 AND -LOCK AND HRQDMA) OR (NOT (-DMACS' OR -XIOW')) (U90 is 2-input OR gates, probably a 74LS32). In other words, this input is forced high when writing to the DMA controller registers (IO ports 0x00-0x1f: the 8237). The output Q3 from U88 goes through a couple more flip-flops to HOLDA (the hold acknowledge input to the 8237). There might be some slight timing differences visible to software due to this change, but it would only be when writing to these registers if at all.
So what I think this is is some logic to fix a race condition between the CPU and the DMA controller. I suspect there was a rare situation where the CPU writes something to the DMA controller at the same time that a DMA access happens, the CPU and the DMA controller end up waiting for each other and the system locks up completely. That's just a guess though.
The other major difference seems to be the removal of the TD2 7ns delay line which delays the clock input to the 8237. I wonder if this was an earlier (and not completely reliable) method of solving the same problem. I don't think this difference would be visible to software since 7ns is so much shorter than a clock cycle, but I suppose it could be if it causes DMA accesses to happen a cycle later.
If anyone else has any more concrete information about these changes, I'd be fascinated to hear it.
In the first revision, input D3 to U88 is -S0 AND -S1 AND -LOCK AND HRQDMA. In the second revision, this is changed to (-S0 AND -S1 AND -LOCK AND HRQDMA) OR (NOT (-DMACS' OR -XIOW')) (U90 is 2-input OR gates, probably a 74LS32). In other words, this input is forced high when writing to the DMA controller registers (IO ports 0x00-0x1f: the 8237). The output Q3 from U88 goes through a couple more flip-flops to HOLDA (the hold acknowledge input to the 8237). There might be some slight timing differences visible to software due to this change, but it would only be when writing to these registers if at all.
So what I think this is is some logic to fix a race condition between the CPU and the DMA controller. I suspect there was a rare situation where the CPU writes something to the DMA controller at the same time that a DMA access happens, the CPU and the DMA controller end up waiting for each other and the system locks up completely. That's just a guess though.
The other major difference seems to be the removal of the TD2 7ns delay line which delays the clock input to the 8237. I wonder if this was an earlier (and not completely reliable) method of solving the same problem. I don't think this difference would be visible to software since 7ns is so much shorter than a clock cycle, but I suppose it could be if it causes DMA accesses to happen a cycle later.
If anyone else has any more concrete information about these changes, I'd be fascinated to hear it.