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XT IDE port mappings...

prime

Experienced Member
Joined
Sep 20, 2009
Messages
153
Location
Coventry, UK
Hi All,

I'd like to try implementing the XT IDE hardware in MESS, possibly along with a new PC clone variant with the Anonymous bios, so we have an emulation the the PC-RETRO kit.

Can someone remind me of the port mapping of the XT-IDE, also what is the difference between the V1 and V2 boards ?

Cheers.

Phill.
 
On V1, ISA A0..A2 drive IDE A0..2, and IDE CS0 is via 300(-307)h. ISA A3 inverts CS0 and CS1.

Then Chuck-mod (implemented in the V2) swaps A0 and A3, i.e. ISA A3 drives IDE A0 and ISA A0 inverts IDE CS0 and CS1.

HTH
 
Last edited:
Then Chuck-mod (implemented in the V2) swaps A0 and A4

Not A0 and A4. It swaps A0 and A3.

Just to make things easier, this is how IDE registers are mapped (offset from base port):
IDE RegisterXTIDE rev 1rev 2 or modded rev 1
Data (XTIDE Data Low)00
Error (in), Features (out)18
Sector Count22
Sector Number / LBA bits 0...7, LBA48 bits 24...31310
Low Cylinder / LBA bits 8...15, LBA48 bits 32...3944
High Cylinder / LBA bits 16...23, LBA48 bits 40...47512
Drive and Head Select / LBA28 bits 24...2766
Status (in), Command (out)714
XTIDE Data High81
Alternative Status (in), Device Control (out)147
 
Doh! Mad bad - glad someone is paying attention :) I've updated my original post.
 
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