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Trident VGA and IBM PC

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    #16
    Yes, please tell the story, because my English very bad. The only thing I can say that the fix is not easy. You need an additional circuit and cut trace on Trident board.



    As you can see, addition board at left bottom corner fix the problem.

    Comment


      #17
      Uhm, I just found a funny mistake on that project's website:
      "Supports 256 MiB or 512 MiB video memory using two or four 256 Mbit x 4 DRAM ICs."
      Made me think about using CUDA with an 8088

      Anyway, I'm also interested in the story, of course!

      Comment


        #18
        Everything started while I was troubleshooting very weird behavior of my universal card. Finally in order to troubleshoot a software (as I thought at that moment) issue I had to use a logic analyzer. The picture of one specific signal (B)ALE was different, than I expected (this is a picture of "jmp $", running between addresses D000A - D000C):

        bus.jpg

        On this picture the ALE just before the time stamp 1216 appeared to be in a wrong place - way before "its" address D000A (time stamp 1246). I knew that the address 0CB97 between the ALE and "its" address was a memory refresh cycle, but couldn't figure how the DMA cycle did manage to get inserted inside of another cycle ??? Luckily a fellow Vic3Dexe from another forum kindly reminded me, that the DMA cycle for the memory refresh logic is not "real" DMA cycle, but rather a "wait state" delay cycle. Of course, this explained everything... At that moment, my card used ALE signal to latch the address bus for own needs, but during the refresh cycle the latched address was completely wrong ! I introduced a minor change to my FPGA design eliminating ALE usage, and everything started working flawlessly. Of course, it raised another question - why do they even need ALE signal on the bus at all, if it's impossible to use ???

        And then here comes the Tronix ! He somehow connected the abovementioned issue with Trident 9000 issues in old PCs. From this point Tronix took things into his hands, so I'm just telling his story...

        Quick look at working (in old PC) and not working Tridents immediately revealed the absence of ALE signal on working adapters. Probably, even then we already could safely assume that the ALE is the reason, but Tronix decided to prove it completely. First step was to increase the interval between memory refresh cycles on his PC clone. And the miracle happened - previously completely dead Trident card started waking up ! Longer refresh interval could provide enough time for the card to start.

        After that, small board was designed and assembled to generate a substitute for the ALE:

        schem.jpg

        After a bit torture to the Trident (cutting off the ALE line and connecting Tronix' board) everything started working completely reliably.

        Bottom line - PCs with "old style" memory refresh logic don't work with cards that require ALE signal. Newer PCs either handle a memory refresh differently, or don't need it at all - Sergey's XT project uses static memory, no refresh required.

        The fix... For existing adapters, it's a bit ugly - requires cutting lines and attaching a small board. For Sergey's SVGA card - a small addition can be easily introduced to the design, that makes the card compatible.

        The end
        Attached Files
        Last edited by newold86; November 6, 2017, 05:40 AM.

        Comment


          #19
          More shortly - all this additional board does is prolongates back front of BALE signal to the front of /MEMRD (or /MEMWR, /IORD, /IOWR) signal, so the card can latch correct address from bus (and not that from DMA).
          BusALE.jpg

          Comment


            #20
            That is a good find and easy to implement in Sergey's design

            Also what is that red motherboard in your photo? it looks awesome

            Comment


              #21
              Originally posted by pietja View Post
              Also what is that red motherboard in your photo? it looks awesome
              This is new replica of the old Soviet computer named Poisk-2. Full length AT mainboard based on KM1810VM86M (8086) CPU with some usable things, such us 2 Mb onboard RAM (640Kb base memory and ~1400Kb for EMS), onboard RTC. BIOS contain "Set-Up" program like "Set-Up" in AT class machines for configure Time, Date, FDD, HDD and other settings. Also for some reasons BIOS contain build-in memory remapping procedures. When one of the DRAM chips is out of order, BIOS correct buildin "DRAM deffect map" and shift up logical memory space up. Thus, computer still usable. KM1810VM86M processor is not 100% clone Intel 8086. He contain some 80186 instruction (pusha, popa) and one very important thing - when invalid opcode occured he generate exception. Therefore, there are 80286 processor emulators exist.

              There is description with photos about replica creation: https://geektimes.ru/post/294155/ (in Russian languarge). Project now open-source. Gerber, circuit and other files here: https://github.com/Haper/poisk-2-mainboard .

              Comment


                #22
                I have designed a simple modchip style board based on the circuit Tronix posted on nedopc.org
                Its designed with 5 SMD parts so that you can stick the board with some dual sided tape on your VGA card.

                I have uploaded the board to OSH park and it should cost only $2.60 for 3 but its not tested!
                https://oshpark.com/shared_projects/r7J7OVea
                VGA_FIX.jpg

                Comment


                  #23
                  delete pls
                  Last edited by Tronix; November 6, 2017, 05:06 AM.

                  Comment


                    #24
                    Interesting stuff! Now that you mention it, I can see the same thing on my XT with my ISA bus sniffer card. Looking through the 5160 technical reference, it seems like none of the IBM cards use ALE (except the extender and receiver cards, which just replicate it onto the expansion unit). http://pinouts.ru/Slots/ISA_pinout.shtml says "This signal is forced high during DMA cycles." but that's clearly not true for 5150/5160 - it must have been a change made in later machines, after the original ALE signal was found to be useless.

                    So the mystery is why IBM put a signal on the bus that wasn't actually usable for anything. I guess the answer must be that they mistakenly thought it would be useful and it was a signal that they were generating anyway so it didn't cost anything to expose it.

                    Comment


                      #25
                      Originally posted by reenigne View Post
                      Ithey mistakenly thought it would be useful
                      Maybe it supposed to be useful for pre-DMA era? I mean - when there is no DMA on the bus, back front of (B)ALE is good to latch and decode address. But even in this case front of /MRD (/MWR etc) is much more suitable for me.

                      Comment


                        #26
                        Originally posted by Xacalite View Post
                        Uhm, I just found a funny mistake on that project's website:
                        "Supports 256 MiB or 512 MiB video memory using two or four 256 Mbit x 4 DRAM ICs."
                        Made me think about using CUDA with an 8088
                        Fixed that, also added a note about IBM PC not working...

                        Comment


                          #27
                          Originally posted by newold86 View Post
                          Everything started while I was troubleshooting very weird behavior of my universal card. Finally in order to troubleshoot a software (as I thought at that moment) issue I had to use a logic analyzer. The picture of one specific signal (B)ALE was different, than I expected (this is a picture of "jmp $", running between addresses D000A - D000C):

                          [ATTACH=CONFIG]41760[/ATTACH]

                          On this picture the ALE just before the time stamp 1216 appeared to be in a wrong place - way before "its" address D000A (time stamp 1246). I knew that the address 0CB97 between the ALE and "its" address was a memory refresh cycle, but couldn't figure how the DMA cycle did manage to get inserted inside of another cycle ??? Luckily a fellow Vic3Dexe from another forum kindly reminded me, that the DMA cycle for the memory refresh logic is not "real" DMA cycle, but rather a "wait state" delay cycle. Of course, this explained everything... At that moment, my card used ALE signal to latch the address bus for own needs, but during the refresh cycle the latched address was completely wrong ! I introduced a minor change to my FPGA design eliminating ALE usage, and everything started working flawlessly.
                          Actually, on both IBM PC and IBM XT all DMA cycles, not only memory refresh cycles, are performed this way - by inserting wait cycles to stop the CPU.
                          The reason for this is that in these systems 8088 runs in so called maximum mode, using 8288 bus controller. In this mode neither processor, nor bus controller generate HOLD/HLDA signals required for 8237 DMAC. Instead 8088 implements a fairly complicated arbitration protocol to support additional bus masters, for example 8087 or 8089.
                          Now, IBM could have used 8089, or at least implemented the 8088 maximum mode arbitration protocol using logic ICs, but instead they just used wait logic to stop the CPU during DMA.

                          Generally speaking, the DMA implementation in IBM PC (and XT, and AT) is pretty much broken... Sometimes I wonder why they even went through the trouble of implementing DMA.

                          Of course, it raised another question - why do they even need ALE signal on the bus at all, if it's impossible to use ???
                          Comparing PC schematic vs. XT schematic - the ALE is implemented in exactly the same way - it is connected directly to the 8288 bus controller. So it is likely that the differences in behavior are the result of the wait logic implementation differences between PC and XT. Quite possible that wait logic was broken (as far as ALE timing goes) on PC, and IBM fixed it in XT...

                          ALE is really comes useful in AT type of systems, that provide unlatched LA17-LA23 signals. In this case ALE is needed to determine when the address is valid. Technically, either on XT or AT, it also allows determining that address is valid sometime before /MEMR, /MEMW, /IOR, or /IOW go active.

                          Comment


                            #28
                            Originally posted by Vic3Dexe View Post
                            More shortly - all this additional board does is prolongates back front of BALE signal to the front of /MEMRD (or /MEMWR, /IORD, /IOWR) signal, so the card can latch correct address from bus (and not that from DMA).
                            [ATTACH=CONFIG]41765[/ATTACH]
                            Nice work!
                            I think it all can be implemented in a single SPLD...

                            Comment


                              #29
                              Originally posted by sergey View Post
                              Quite possible that wait logic was broken (as far as ALE timing goes) on PC, and IBM fixed it in XT...
                              At least it's not fixed in my XT board from DTK. And it's not fixed in your single board XT I'm pretty sure (of course, could be wrong) if you slightly modify your XT to start fake memory refresh cycles, it stops working with your VGA adapter. Too bad it's not very straightforward to conduct this experiment - will require some trace cutting and soldering...

                              Comment


                                #30
                                Originally posted by newold86 View Post
                                At least it's not fixed in my XT board from DTK. And it's not fixed in your single board XT I'm pretty sure (of course, could be wrong) if you slightly modify your XT to start fake memory refresh cycles, it stops working with your VGA adapter. Too bad it's not very straightforward to conduct this experiment - will require some trace cutting and soldering...
                                But it works on most XT's, including the original IBM XT

                                And I am not quite sure what is broken on my XT... Can you elaborate?

                                Comment

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