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Any interest in a PCjr CPU upgrade board?

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  • eeguru
    replied
    Also I purchased a BGA rework machine earlier in the year for some of my engineering consulting projects. When I did that, it vastly increased my confidence mounting and using BGA parts in both my work projects and hobby projects. That opened up a world of possibilities. I created a comparison spreadsheet to look at all the currently available part offerings on Digikey. I'll link it below in case it's useful to you (or anyone else). The pricing is typically for lowest speed grade parts except where noted. All in quantity 1. It has a few sortable columns that help compare options on gate and storage density or per $ - although this is largely an apples/oranges comparison (eg. Series 7 6-input/2-output LUT is not even close to, for example, any Lattice cell architecture - which is vastly different than a multi-role cell of a Microsemi/Microchip part, etc).

    https://www.retrotronics.org/vcf/fpg...ysis_2019.xlsx

    Edit: I also limited it to those parts supported by the free to use license from the vendors in their proprietary tool chains - or parts well supported by open tool chains (eg ECP5, iCE40, etc). Series 7 parts are now well supported by FOSS chains now, but I haven't followed the development as closely as ECP5, etc.
    Last edited by eeguru; August 27, 2020, 01:43 PM.

    Leave a comment:


  • eeguru
    replied
    Here is an image export of the BGA break-out and position test it did a while back for such a project. Everything fits in the outline of the overlayed PTH dip socket offset by 50 mils with its pins bent around the board and soldered underneath.

    https://retrotronics.org/vcf/inline_test.png

    Leave a comment:


  • MicroCoreLabs
    replied
    Actually I was thinking sub $100... As you said, there's probably no point if it is too expensive... The FPGA is <$20, SRAM is <$5, so total COGS could be around $50... It would be an experiment in frugality though...

    I have written BIU's - Bus Interface Units - for both min and max mode, so it has been used in place of the CPU in the 5150/5160 and other 4.77Mhz XT's. If you recall it is the only FPGA core which can run your 8088 MPH demo!

    That said, when I "unlock" the cycle accuracy it becomes faster, just not jaw-dropping fast... 2X if I recall. Thats cool I guess.. Is there more interest in this?

    The reason the PCjr is more interesting is because there is no DMA, so all memory accesses are initiated by the CPU, and I am able to locate it all inside/beside the FPGA itself and can run at 100Mhz, or an order of magnitude faster than physical DRAM... This is how I achieved the 3-4X speed improvement on my PCjr prototype... 128K was running inside of the FPGA... Being able to locate the BIOS ROMS and cartridges would also give it a speed boost...

    A max-mode version can definitely be created which has the ability to run cycle accurate and "unlocked" for a speedup. I was thinking a fun feature would be to have *all* BIOSes for each 5150/5160 version as well as the test BIOSes and others all selectable by the FPGA.. maybe by jumper setting or register access, or uploading realtime then booting into the new BIOS... This is something I did when developing the core and was a cool feature!

    Thanks,
    -Ted

    Leave a comment:


  • eeguru
    replied
    I had been considering such a project for some time - but I have very limited time atm. So other big projects of mine have been sidelined due to that so far. But I still revisit this idea from time to time. I think I saw where you recently open released your MCL86 micro-coded CPU. Thanks for that. But I was originally going to use a more straight forward next186. I even did some layout tests to see what was possible.

    My principle goals were size and cost. For size I wanted to fit it into a ~500 mil width PCB with Batten-Allen J-lead dip pins like these:

    http://www.dasarodesigns.com/product...dge-clip-pins/

    That would allow it to fit into the form factor of the standard 8088 socket - a true DIP form-factor replacement. Otherwise you might get clearance issues with the direction of the PCB expansion in systems other than the PCjr. With those pins, one could even wrap around another PTH DIP socket on top of the PCB and place the original 8088 in it - a double stacked sandwich. A switch or FPGA GPIO could hold the real CPU in reset (assuming it tri-states all of its pins) and vice-versa for compatibility. But it means you have to a) constrain the chips on top to the voids left in the middle of the piggy-backed DIP socket (possible - see below) and it doesn't leave a lot of room for external sockets and connectors. Though a micro-SD card slot could fit underneath or at an end.

    For cost mitigation and to meet the width constraint of 500 mils, about the only FPGA that will fit into that space with a ball pitch of at least 0.8mm is an iCE40HX8K. That's only 7680 4-input LUTs and FFs. Should fit most x86 cores including yours. It only has 128 Kbits of RAM (32 reconfigurable 4 Kbit EBRs). Enough for your micro-code, for example, and a storage option ROM (sd-card) but not much else. Upside is it's really cheap (and fits!). Bigger FPGAs come in similar packages but with 0.5mm pitch or less. That requires a more expensive PCB - either in DRC limits, blind/burred vias, or via in pads. It is also desirable to keep all the components on one side - which I think is possible given by test layout research.

    TI makes some nice dual voltage rail '245s that I use for a lot of 5V translation projects. They would fit nicely too. We can also get up to 2MB of SRAM @ 10ns and 8MB of PSRAM @ 70ns in a small 49-pin BGA, both at 16-bits wide, with a .75mm pitch. I lean more towards the SRAM - maybe even in a smaller/cheaper capacity - with the faster cycle time. As you mentioned, having local RAM and shadow ROM running in lock step with the CPU will vastly increase the overall performance. You have to be careful of the lower 128KB though. It's shared as video RAM with the display controller. So you have to snoop accesses to the video page registers and redirect memory accesses to video frame buffers off-chip for the current page.

    A dip switch or jumper would have to be added to disable local RAM and any ROM shadowing for compatibility sake. And a configuration interface at an I/O port could reconfigure local ram/shadow/other features/etc.

    The PCjr is a minimum mode implementation of the 8088. But I don't see any reason why it wouldn't work in a maximum mode system or with an extra bus buffer - a 8086 socket/mode with some BIU changes. However the PCjr (and Tandy 1000) is somewhat unique in that they both do not have a DMA controller. For DMA operation, either local/on-board RAM has to be disabled entirely, or you'd have to only shadow real memory available in the system while snooping on the the DMA page and address registers redirecting memory access off-board after a transfer takes place.

    Challenge is to not create feature creep by sticking to a minimum spec for Rev.A - then build from there once working. And secondly to keep cost down. I can reliably mount BGAs here at home now. I can build prototypes or even design a board if you want to work at the RTL level.

    -A
    Last edited by eeguru; August 27, 2020, 01:12 PM.

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  • Trixter
    replied
    As someone who thinks this project is cool, I cheer you on from the sidelines. However, I'm not sure I could pony up $200+ for a board.

    Is there anything that limits it to the PCjr? Asking because it might be interesting to see if your replacement could be made generic enough to replace any 4.77 MHz 8088 in any system.

    Leave a comment:


  • MicroCoreLabs
    started a topic Any interest in a PCjr CPU upgrade board?

    Any interest in a PCjr CPU upgrade board?

    I was thinking of making a small board which could replace the 8088 on the PCjr and wanted to see if there was any interest...

    Basically it would contain an FPGA running the MCL86 CPU core which could be set to cycle accurate mode or set to "unlocked" which runs much faster. A 512KB SRAM chip would bring the total memory to 640KB and could run at the 100Mhz core's speed.

    This would be an integration of a project I did a few years ago... See links below...

    To spice things up, a second 128KB SRAM could be added in the address range of the two PCjr cartridges, so we could upload the images to the SRAM via diskette/JrIDE, then after resetting the machine, it would wake up with the cartridge(s) installed...

    In theory, the PCjr's BIOS could also held in SRAM... So after first boot we could upload the new BIOS to SRAM and have the FPGA boot from this alternate image after reset... for those who dream of rolling their own PCjr BIOS!


    Anyway, I had fun with this project as a prototype... The FPGA held 128KB of the PCjr's RAM, and was cycle "unlocked", so it yielded a PCjr which was faster than a PCAT!


    Thoughts/ideas?

    Thanks,
    -Ted

    https://microcorelabs.wordpress.com/...-fastest-pcjr/
    https://microcorelabs.wordpress.com/...imum-more-biu/
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