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Any interest in a PCjr CPU upgrade board?

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    Any interest in a PCjr CPU upgrade board?

    I was thinking of making a small board which could replace the 8088 on the PCjr and wanted to see if there was any interest...

    Basically it would contain an FPGA running the MCL86 CPU core which could be set to cycle accurate mode or set to "unlocked" which runs much faster. A 512KB SRAM chip would bring the total memory to 640KB and could run at the 100Mhz core's speed.

    This would be an integration of a project I did a few years ago... See links below...

    To spice things up, a second 128KB SRAM could be added in the address range of the two PCjr cartridges, so we could upload the images to the SRAM via diskette/JrIDE, then after resetting the machine, it would wake up with the cartridge(s) installed...

    In theory, the PCjr's BIOS could also held in SRAM... So after first boot we could upload the new BIOS to SRAM and have the FPGA boot from this alternate image after reset... for those who dream of rolling their own PCjr BIOS!


    Anyway, I had fun with this project as a prototype... The FPGA held 128KB of the PCjr's RAM, and was cycle "unlocked", so it yielded a PCjr which was faster than a PCAT!


    Thoughts/ideas?

    Thanks,
    -Ted

    https://microcorelabs.wordpress.com/...-fastest-pcjr/
    https://microcorelabs.wordpress.com/...imum-more-biu/

    #2
    As someone who thinks this project is cool, I cheer you on from the sidelines. However, I'm not sure I could pony up $200+ for a board.

    Is there anything that limits it to the PCjr? Asking because it might be interesting to see if your replacement could be made generic enough to replace any 4.77 MHz 8088 in any system.
    Offering a bounty for:
    - A working Sanyo MBC-775 or Logabax 1600
    - Music Construction Set, IBM Music Feature edition (has red sticker on front stating IBM Music Feature)

    Comment


      #3
      I had been considering such a project for some time - but I have very limited time atm. So other big projects of mine have been sidelined due to that so far. But I still revisit this idea from time to time. I think I saw where you recently open released your MCL86 micro-coded CPU. Thanks for that. But I was originally going to use a more straight forward next186. I even did some layout tests to see what was possible.

      My principle goals were size and cost. For size I wanted to fit it into a ~500 mil width PCB with Batten-Allen J-lead dip pins like these:

      http://www.dasarodesigns.com/product...dge-clip-pins/

      That would allow it to fit into the form factor of the standard 8088 socket - a true DIP form-factor replacement. Otherwise you might get clearance issues with the direction of the PCB expansion in systems other than the PCjr. With those pins, one could even wrap around another PTH DIP socket on top of the PCB and place the original 8088 in it - a double stacked sandwich. A switch or FPGA GPIO could hold the real CPU in reset (assuming it tri-states all of its pins) and vice-versa for compatibility. But it means you have to a) constrain the chips on top to the voids left in the middle of the piggy-backed DIP socket (possible - see below) and it doesn't leave a lot of room for external sockets and connectors. Though a micro-SD card slot could fit underneath or at an end.

      For cost mitigation and to meet the width constraint of 500 mils, about the only FPGA that will fit into that space with a ball pitch of at least 0.8mm is an iCE40HX8K. That's only 7680 4-input LUTs and FFs. Should fit most x86 cores including yours. It only has 128 Kbits of RAM (32 reconfigurable 4 Kbit EBRs). Enough for your micro-code, for example, and a storage option ROM (sd-card) but not much else. Upside is it's really cheap (and fits!). Bigger FPGAs come in similar packages but with 0.5mm pitch or less. That requires a more expensive PCB - either in DRC limits, blind/burred vias, or via in pads. It is also desirable to keep all the components on one side - which I think is possible given by test layout research.

      TI makes some nice dual voltage rail '245s that I use for a lot of 5V translation projects. They would fit nicely too. We can also get up to 2MB of SRAM @ 10ns and 8MB of PSRAM @ 70ns in a small 49-pin BGA, both at 16-bits wide, with a .75mm pitch. I lean more towards the SRAM - maybe even in a smaller/cheaper capacity - with the faster cycle time. As you mentioned, having local RAM and shadow ROM running in lock step with the CPU will vastly increase the overall performance. You have to be careful of the lower 128KB though. It's shared as video RAM with the display controller. So you have to snoop accesses to the video page registers and redirect memory accesses to video frame buffers off-chip for the current page.

      A dip switch or jumper would have to be added to disable local RAM and any ROM shadowing for compatibility sake. And a configuration interface at an I/O port could reconfigure local ram/shadow/other features/etc.

      The PCjr is a minimum mode implementation of the 8088. But I don't see any reason why it wouldn't work in a maximum mode system or with an extra bus buffer - a 8086 socket/mode with some BIU changes. However the PCjr (and Tandy 1000) is somewhat unique in that they both do not have a DMA controller. For DMA operation, either local/on-board RAM has to be disabled entirely, or you'd have to only shadow real memory available in the system while snooping on the the DMA page and address registers redirecting memory access off-board after a transfer takes place.

      Challenge is to not create feature creep by sticking to a minimum spec for Rev.A - then build from there once working. And secondly to keep cost down. I can reliably mount BGAs here at home now. I can build prototypes or even design a board if you want to work at the RTL level.

      -A
      Last edited by eeguru; August 27, 2020, 01:12 PM.
      "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

      Comment


        #4
        Actually I was thinking sub $100... As you said, there's probably no point if it is too expensive... The FPGA is <$20, SRAM is <$5, so total COGS could be around $50... It would be an experiment in frugality though...

        I have written BIU's - Bus Interface Units - for both min and max mode, so it has been used in place of the CPU in the 5150/5160 and other 4.77Mhz XT's. If you recall it is the only FPGA core which can run your 8088 MPH demo!

        That said, when I "unlock" the cycle accuracy it becomes faster, just not jaw-dropping fast... 2X if I recall. Thats cool I guess.. Is there more interest in this?

        The reason the PCjr is more interesting is because there is no DMA, so all memory accesses are initiated by the CPU, and I am able to locate it all inside/beside the FPGA itself and can run at 100Mhz, or an order of magnitude faster than physical DRAM... This is how I achieved the 3-4X speed improvement on my PCjr prototype... 128K was running inside of the FPGA... Being able to locate the BIOS ROMS and cartridges would also give it a speed boost...

        A max-mode version can definitely be created which has the ability to run cycle accurate and "unlocked" for a speedup. I was thinking a fun feature would be to have *all* BIOSes for each 5150/5160 version as well as the test BIOSes and others all selectable by the FPGA.. maybe by jumper setting or register access, or uploading realtime then booting into the new BIOS... This is something I did when developing the core and was a cool feature!

        Thanks,
        -Ted

        Comment


          #5
          Here is an image export of the BGA break-out and position test it did a while back for such a project. Everything fits in the outline of the overlayed PTH dip socket offset by 50 mils with its pins bent around the board and soldered underneath.

          https://retrotronics.org/vcf/inline_test.png
          "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

          Comment


            #6
            Also I purchased a BGA rework machine earlier in the year for some of my engineering consulting projects. When I did that, it vastly increased my confidence mounting and using BGA parts in both my work projects and hobby projects. That opened up a world of possibilities. I created a comparison spreadsheet to look at all the currently available part offerings on Digikey. I'll link it below in case it's useful to you (or anyone else). The pricing is typically for lowest speed grade parts except where noted. All in quantity 1. It has a few sortable columns that help compare options on gate and storage density or per $ - although this is largely an apples/oranges comparison (eg. Series 7 6-input/2-output LUT is not even close to, for example, any Lattice cell architecture - which is vastly different than a multi-role cell of a Microsemi/Microchip part, etc).

            https://www.retrotronics.org/vcf/fpg...ysis_2019.xlsx

            Edit: I also limited it to those parts supported by the free to use license from the vendors in their proprietary tool chains - or parts well supported by open tool chains (eg ECP5, iCE40, etc). Series 7 parts are now well supported by FOSS chains now, but I haven't followed the development as closely as ECP5, etc.
            Last edited by eeguru; August 27, 2020, 01:43 PM.
            "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

            Comment


              #7
              Regarding the next186... There are a number of x86 cores which will run as fast as the FPGA technology allows... >160Mhz in next186's case? But in my opinion it is more interesting and challenging to have the core be cycle accurate and then run it in the original vintage hardware like the IBM and compatible computers. Only then can you be sure the core is actually correct in both the implementations of the instruction set and the structural features like prefetch queues, interrupt priority ordering, prefixes, arbitration, etc... It is unlikely that the rtl cores can replace the actual 8088 as the MCL86 can...

              I am curious if the next186 can run the test code I uploaded to GitHub... I developed and ran these tests to exercise every opcode and addressing mode of the MCL86 core... It runs successfully on both the real x86 and the MCL86...

              In fact... one thing I ran into when porting it to the PCjr was the fact that I *needed* to run cycle accurate during POST... When I ran it "unlocked" I got a beep and no splash screen. What I needed to do was run it cycle accurate until after the POST, then as soon as an NMI occurred (a PCjr key was pressed) I would then disable the cycle accuracy!

              Anyway.. just a note that cycle accuracy is needed at times and that the "rtl" FPGA cores generally won't work... Even 8088 MPH also won't begin if it senses the CPU is not cycle accurate!

              Comment


                #8
                Originally posted by eeguru View Post
                The PCjr is a minimum mode implementation of the 8088. But I don't see any reason why it wouldn't work in a maximum mode system or with an extra bus buffer - a 8086 socket/mode with some BIO changes. However the PCjr (and Tandy 1000) is somewhat unique in that they both do not have a DMA controller.
                Since "Tandy 1000" came up I'll throw in that an accelerator like this would have a lot of potential for the original 8088 Tandy 1000s, especially the oddball EX/HX models for which no other practical options currently exist. In those machines you would be dealing with some pretty severe space constraints, both horizontally and vertically, so a miniaturized DIP-size package would have a lot of advantages as long as it could be made short enough to clear an installed PLUS card sitting overhead.

                (Of course one of the complications with a Tandy 1000 is it *may* have a DMA controller; an original conventionally slotted one almost certainly will because 128k didn't go that far even when they were new. You could of course pull it out in all the 8088 T1000s except the SX if you had RAM on the accelerator, though in an EX or HX you might need to sub a different DMA-less board to continue supplying a Plus-slot breakout for additional expansion.)

                Just spitballing, here's another idea for Tandy 1000s, if there's someone who has the assembly-language chops: normally in the 8088 machines you can only add expansion memory up to 640k minus however much RAM is onboard and connected to the video controller. (Either 128k or 256k) This means that these machines always lose at least 16k of DOS memory to video requirements, and it also means in the 7.16mhz machines a chunk of memory is a lot slower than the expansion RAM. (If some benchmarking I've done is correct the RAM built into an 1000EX or HX effectively only runs at 4.77mhz.) The memory tests loop in these machines only counts up to 384k/512k of expansion memory and will insist on this sharing behavior even if you were to stick a full 640k in. However the 80286-powered Tandy 1000 TX's motherboard, which with its normal complement of 512k "fast ram" and 128k video RAM behaves the same way, also allowed sticking in an addition 128k of fast RAM, and if it detects it on power-up the BIOS programs the video chip so the memory behind it no longer appears in the base 640k window and is only paged around the B0000-BFFFF area. I know from some crude experimentation that at least the EX and HX (and presumably the SX, since they all use the same chipset) appear to support in hardware programming the video hardware the same way. (It's in the technical manuals as well; the details are a little piecemeal but if you combine the info from about three different sources it's all there.) I don't know if you can do the same trick with the original 1000s with discrete video, however. Don't have one to fool with.

                Anyway, what would be a neat trick is if a smart person could analyze the differences between the RAM test and video setup/mode switching areas of the EX/HX/SX BIOSes and the TX BIOS and produce a patched 8088 BIOS that would recognize a 640k base RAM upgrade and configure the video chipset accordingly. For an accelerator like that described it'd be a significant boon since you'd be free to ignore all the complications that otherwise arise if you try to "overlay" fast memory on top of the built-in RAM that's pulling double-duty as VRAM and system RAM. VRAM would just be VRAM, like a regular video card.

                An HX or EX with an accelerator that can speed it up to the 286-like speeds that it can apparently achieve in a PCjr would be a really desirable machine for playing Tandy 1000-specific games. (As it stands the 8088-powered machines tend to be a little on the slow side.)
                My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                Comment


                  #9
                  https://www.ebay.com/itm/IBM-PCjr-HO...UAAOSw5PhfFfvo


                  This 40-pin "underside" socket looks interesting. I wonder if it is off-the-shelf or something they custom made.

                  Comment


                    #10
                    Maybe the photo isn't clear enough to be sure, but it looks like that's made out of machine pins. Plugging something like that into the standard cheap wiper sockets tends to kind of mess them up if you ever want to put the original CPU back in.
                    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                    Comment


                      #11
                      You can buy those headers from Digikey/Mouser. I sell a machine pin version in my store:

                      http://store.go4retro.com/ic-header/

                      The pins on these are very narrow, and do not affect cheap wiper sockets. But, you can also buy the flat pin versions (they cost more):

                      https://www.digikey.com/products/en/...=1&pageSize=25

                      Aries sells them (looks like they only have forked pin option at Digikey, but they sell the simple post version as well. I used to buy them, and they work fine.

                      Comment


                        #12
                        Nice headers... I think one of those should work!

                        Just brainstorming, but since a 512KB SRAM would be attached to the FPGA and available to the CPU, in theory a portion of it could be optionally remapped to cover, among other things, the extension BIOS address range so the Universal XTIDE BIOS could be used.

                        After the initial PCjr boot the address range would be populated by software on diskette. It would then jump to the cold-reset vector so the new ROM(s) would be detected by the PCjr's BIOS.

                        If there was a CF header on the board it would allow hard drive functionality similar to jr-IDE...

                        Comment


                          #13
                          Sorry for jumping in late. Im interested. I have 4 pcjrs

                          Comment


                            #14
                            Yeah I'm late to the game but I'd buy this if would work with my PS/2 model 25.

                            Comment


                              #15
                              Hi Ted,

                              I'm a big fan of your work. The price is right for such a unique design and I'd take one. But it's basically for giggles ... I have 486 and Pentium machines around. A super fast PCjr is kind of silly. ;-0

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