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Original-IBM-5150 or IBM-Clone Memory Experimentation Thread

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    4164s aren't that common, you should really learn proper technique with the vacuum desoldering tool. Reflowing the joints first with fresh solder is a big thing


      I did it. 3 days of work.


      My neck hurts, my hand hurts. :P

      There's some negligible damage, but ONLY to the solder mask. I have some mask-repair paint on the way to touch up some of the surface.

      I had to use two soldering irons at times, plus a micro drill bit (i.e. 0.4mm) for the more-stubborn holes. (mostly those connected to a ground or A8 [address line 8] plane, that would wick up the heat.)

      I made sure not to keep the iron on the holes too long, and I checked that the copper inside and on the surface were flush with the board. (to make sure that the epoxy holding them did not loosen)

      I didn't touch the 9th row of memory footprints. I'm not sure what use parity memory has in this case. I know what it's for, I just don't see any real use for it, unless it adds more integrity for memory contention. (I could add something later, since I stated earlier that this sister board has a space for a parity generator chip.)


        The mask repair paint is still on the way, as well as an ultraviolet flashlight to cure the paint when finished.

        I also did a bit of snooping around on minuszerodegrees, and found this:

        If I had to guess, given what I've seen in my Sanyo, and what I've discussed with this forum, my system is closer to an IBM 5160 than a 5150 or 5170. There's only one set of 8 DIP switches, as described on the MZD page about the 5160, and the document in the page above describes the EXACT modification that I'm attempting to do. (Although I have to look closer at the document to see how similar it is to my system, barring component numberings)
        Last edited by T-Squared; October 26, 2020, 07:09 PM.


          I'm curious to know one thing, did any XT/AT clones have PLAs installed?

          The reason why I ask is because IBM had PLAs in their systems, but most of what I see on my Sanyo's CPU/Memory board is logic ICs.


            Originally posted by T-Squared View Post
            I'm curious to know one thing, did any XT/AT clones have PLAs installed?
            Yes, but of course that doesn't mean all of them did. And this is where you're going to have to bite the bullet and suss out exactly how the memory addressing circuitry on your machine works because, as I noted earlier, if you don't tweak that then the 256kb chips will just be enabled for the same address ranges as the 64kb ones were.

            The most straightforward methods of decoding memory without PLAs tend to involve 74LS138 and 74LS139 decoder/demultiplexers. For instance, just spitballing here's how you could do the chip selects for 256k of RAM made up of 4164's in an 8088 with a single '139:
            • Connect pins 2 and 3 to A18 and A19 and pin 1, chip enable for the first decoder, to ground
            • Connect the output at pin 4, which will go low when the computer is in the lowest 256k of address space, to pin 15, enable for the second decoder.
            • Connect pins 14 and 15, inputs for the second decoder, to A16 and A17.
            • Use the four outputs on pins 9-12 as the chip select for each bank of 64k. (This will run to the multiplexing circuitry that handles the RAS/CAS generation.)

            The fact that Sanyo *seemingly* built the board with the intention of allowing the option to hold 640k implies that they probably at least ran the traces for something more sophisticated, but the pieces might not be populated and there might be either switches that need to be changed or jumpers/traces that have to be cut to reconfigure it. Look for "something" that's connected to the high address lines that has outputs that ultimately lead to the RAS/CAS circuitry and map it out.
            My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot


              ... per the above, it just occurred to me how you could decode 640k with mixed 256k and 64k DRAMs using the same one Ď139.
              • On the first decoder use the outputs corresponding with 0-256k and 256k-512k directly to enable the two 256k banks.
              • Use the output for 512k-768k as enable for the second decoder.
              • Use the lines that correspond to 512k-576k and 576k-640k as enables for the two 64k banks.

              Not saying Sanyo did that, but itís a method that could be achieved with just a few jumpers.
              My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot


                I do see quite a few 138 chips. Also, I see jumpers on the board that are either unpopulated or unshorted.

                I'll figure it out when I refurbish the board mask.


                  Good news! I've completed the mask repair (The ultraviolet flashlight worked perfectly!) and inserted the memory sockets.

                  Not so good news, I don't have a display yet, because the memory (512kb at the moment) won't work. (I still have to look at the 5160 schematics to redirect the proper signals.) But for now, my mind is fried, and I can't retain the schematic tracings mentally yet.


                    (This will expand as I look at the schematics)

                    Ok, on the memory banks, Pin 1 of all the memory chips ( Address Line 8 ) goes to a resistor that is marked "30". (It's on PDF Page 74 / Book Page 1-52 of the 5160 Technical Reference) I'm a bit confused because I don't know if that means just ohms or kilo-ohms.

                    EDIT: Never Mind, the resistor is indeed 30 ohms. (I measured it with a multimeter)

                    Update: It does indeed seem that Sanyo had intended to make the MBC-775 or (maybe) similar models expandable to 640k. Address Line 8 is attached to the 30 ohm resistor, which is tied to pin 4 of the additional LS158 chip, just like on the 5160 schematic. I'll check the rest of the circuit upwind from that, then see where the buffer delay line needs to go. (I detached that because the factory patch wire leading from the buffer delay line to the LS158 seems to be in a different place on the schematic, and I needed to detach it to clean the final through-hole and insert the chip socket for the LS158.)

                    Update 2: Ok, the 158-to-buffer-delay-line wire should stay where it was. (It's ok, I've been taking pictures before I change anything, to prevent problems in reversing small mistakes)

                    On the other hand, it's odd, because the delay line IC in my Sanyo does not match the schematic exactly. It's actually supposed to be on Pin 3 (IBM) instead of Pin 4 (Sanyo), but the pin for that delay (60ns) is not present:

                    IBM's Pins (TTLDL-20):
                    12: 20ns
                    4: 40ns
                    3: 60ns
                    6: 80ns
                    5: 100ns

                    Sanyo's Pins ( 201JHT1006L, assuming equal divisions, because the datasheet does not have delay markings, and this was the only datasheet I could find!):
                    11: 25ns
                    4: 50ns
                    10: 75ns
                    5: 100ns

                    EDIT: I'm also assuming that the memory bank CLOSEST to the CPU is bank 0? (I'm checking if I have the memory ICs in the correct sockets.)
                    Last edited by T-Squared; October 29, 2020, 09:44 AM.


                      RN3 is 30R = 30 Ohms.

                      Looked in my 5160 at Rn3


                        Ok, I've run into a small problem. The A/B inputs of the extra 158 are not connected to any of the Y outputs of any 244 chip.

                        According to the schematic, they should be tied to a 244 chip that is grounded. I don't know what ICs they are on my Sanyo yet, but it's easy to figure out. On the IBM, though, they are U14 and U16

                        EDIT: Ok, it seems they are all grounded on the Sanyo.
                        Last edited by T-Squared; October 29, 2020, 11:10 AM.


                          Originally posted by Eudimorphodon View Post
                          ... per the above, it just occurred to me how you could decode 640k with mixed 256k and 64k DRAMs using the same one ‘139.
                          You were talking about this? Guess what I happened to find over near the buffer delay line IC? A footprint for an LS139. That may be what I need.


                            Right now, and for the past day or so, I've been mapping out the connections between the LS158s and the LS244s. (based on the schematics in the 5160 Technical Reference)

                            Some of the pins on the 158s don't go anywhere. I'm wondering if I can use a free LS244 input-pair to tie the memory in properly...


                              At first glance, the memory decoding seems to be controlled by four 224 chips, and two 373 chips. (Along with the 158s and 138s)

                              (Again, this is at first glance. I'm not saying that there are more yet.)


                                Ok, there's three 158 chips, two 138s, four 244s (yeah, I called them 224s by accident), THREE 373s, and three 245s.

                                The thing with this setup is, the way they are wired does not match the schematics of the 5160. Probing the pins of the chips and checking continuity doesn't show the same pathways as the schematics. (I can post my findings later, if you want.)