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Original-IBM-5150 or IBM-Clone Memory Experimentation Thread

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    Here's what I've found so far, based on my continuity checks:

    The resistors that are on Address line 8 for the 256k (64kilobyte) chips are where they should be and at proper values. (They're in the schematic with the 158s below) The buffer delay line is where it should be.

    However, the chips and their setup in decoding the contents of memory seems different, somehow.
    Here's my routing of the pins between the chips (I may have gotten some wrong, because as I routed them, some don't make sense):
    Sanyo Pin Routingflat.jpg

    And the IBM 5160's first stage of the memory-decoding circuitry (158s):

    And its second stage (244s and 373s):
    Last edited by T-Squared; November 2, 2020, 10:11 AM.


      Originally posted by T-Squared View Post
      At first glance, the memory decoding seems to be controlled by four 224 chips, and two 373 chips. (Along with the 158s and 138s)
      I had a longer reply to this typed up, but then I accidentally trashed it because backspace is evil, so here's a shorter version: it feels like you're a little confused what a '244 and '373 do. Neither of these things are "controllers". A '244 is just a unidirectional buffer/line driver; whether it's asserting what it sees on the input or goes into an invisible "tri-state" condition can be switched on and off, but that's it, it doesn't care at all about the contents of the data/address lines piped through it. (Note also that control lines like MEMR/MEMW/whatever are also commonly piped through '244s because a '244 is often employed to increase the TTL "fan out" of a signal that's tapped by many consumers.) A '373 is likewise just a latch; based on the status of a control signal it either transparently rebroadcasts on its output what it sees on its input, or it "freeze-frame"'s it and holds an instantaneous state on the output until the latch signal is released. (The reason the 373's are there is because of the multiplexed bus of the 8088; the same pins are used for addresses and data/status signals at different parts of bus cycle.)

      The "decoder", IE, the thing that decided what bank of memory is active when address "X" appears on the buffered/latched address lines in the 5160 is chip U44, which is a programmed 24S10 1024x4 bit PROM. It's pretty literally a "black box"; its inputs are A16-A19 (which means it has 64k granularity), the state of a couple DIP switches saying whether a given pair of sockets is enabled at all, and some jumpers which I *think* say whether a given pair of banks has 64k or 256k chips in it, and what comes out are some signals that say which of bank 1 through 4 (or none) are turned on. (This part of the schematic is pretty confusing because the four outputs from the PROM are gated in several odd ways and go to both the "Q" inputs and the output enables of the RAS/CAS '138s.) If the Sanyo has a similar PROM, or possibly another programmable device like an early PAL, in this position then your best option is probably to find a compatible part and program it how you need.

      If there is no PROM on the Sanyo board then you need to figure out if they *did* actually make full allowances on the board for the 640k option. This is where putting the manual for the 64k/256k 5150 alongside the 5160's manual will probably be instructive. Compare the memory decoding circuitry and *basically* the difference is instead of the RAS/CAS '138s being directly linked to A16 and A17 (also note they get an input from another '138, U48 who's *actually* ultimately the thing that says RAM should be active in the lowest 256k of space by sitting on A18 and A19) they are "abstracted" through that PROM. IBM didn't have to do it this way; to expand the 5150's decoding to support 256k on a pair of the sockets they could have, for instance, used additional outputs on '138 as inputs to U47 and U65. (I'd need to sit down with a piece of paper to work this out, but I think you could reshuffle it to work, possibly with the addition of a couple of NAND gates.)

      Long story short, I think you need to bite the bullet and actually draw out the schematic of how the Sanyo derives the CAS/RAS signals for each memory bank. If it doesn't use a PROM like the 5160, which there's a good chance it doesn't, you'll need the complete layout of how it is *now* to figure out how to hack it properly.
      Last edited by Eudimorphodon; November 2, 2020, 11:53 AM.
      My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot


        No, I understand that the chips are not controllers.
        I read the datasheets for them. I understand that these chips do some kind of data-scrambling logic and channel-switching "magic" to turn the information in memory into something the CPU understands.

        I'm just contemplating if tying the A16 and A17 data lines into a free spot in the logic circuitry will make it work, like changing how a floppy drive interprets grounded setting pins. (This is tentative, though. I know it might not be as simple as that.) The other data lines seem to be added already.

        Update: Right now, I'm setting up a new pin map to see if I can find a pattern in how the logic lines are connected.
        Last edited by T-Squared; November 2, 2020, 01:15 PM.


          Originally posted by T-Squared View Post
          No, I understand that the chips are not controllers.
          I read the datasheets for them. I understand that these chips do some kind of data-scrambling and channel-switching "magic" to turn the information in memory into something the CPU understands.
          They don't "scramble" anything. The '244 is literally just a valve. (Or maybe "two valves" because it has a separate control "handle" for each 4 bits of the total 8 bits it handles.) The inputs, usually designated "1A(1-4)" and "2A(1-4)" on the datasheets, are controlled by the signals "1G" and "2G" respectively. If the "G" for those four bits is low the input state (high or low) is presented on "1Y(1-4)" or "2Y(1-4)" respectively; if "G" is high the outputs assume a "high impedance" state which essentially renders the device invisible. (Which means a downstream device either gets high or low from another device, a pull up/pull down resistor, or just floats.) When you see a '244 in a circuit the "G"s are often tied to ground, which means it's basically just acting like an "amplifier" for the input signal. If it *is* controlled it's usually because there's something else connected to the output side and the 244' is acting as part of a multiplexer.

          (For instance, a pair of '244s could be used to do roughly the same job as a pair of 74LS157 Quad 2-input multiplexers, IE, either could be used to decide if the 8 bits to be asserted on "Bus Z" were sourced from "source X" or "source Y". The control circuitry would just be slightly different.)

          A '373 does the same thing (IE, it can act as a "valve" because it has an output enable signal to tri-state the output, although in its case it applies to all 8 outputs simultaneously, not two groups of four) except it can also "latch" what's coming out the other side. IE, if output enable is "low" then what comes out on the "O" outputs matches the "D" inputs in real time if latch is "high", but if latch goes "low" the value on D0-7 is latched into into registers "Q0-7", and that value is what comes out on "O0-7" for as long as latch is held low, regardless of what happens to "D0-7". Again, nothing gets "scrambled"

          I'm just contemplating if tying the A16 and A17 data lines into a free spot in the logic circuitry will make it work, like changing how a floppy drive interprets grounded setting pins. (This is tentative, though. I know it might not be as simple as that.) The other data lines seem to be added already.
          No. A16 and A17 are not "data lines", they're address lines, and they're no doubt already "connected to the logic circuitry" that's used to select which set of RAS/CAS lines are active because decoding A16 and A17 is how you tell which page of 64k you're on. (IE, like this: 64K takes 16 bits to represent; IE, if the smallest chips the Sanyo supports are 64K we can completely ignore A0-15. That leaves A16-A19. That's 4 bits, which allows 16 possibilities, which means a total of 16 possible pages of 64k to think about. When you only have 4 banks and they all have 64k then this is what your decoding needs to care about to decode your RAM, which should reside in the bottom 256k of the possible 1024k of address space:

          A19 - Has to be a zero
          A18 - Has to be a zero

          (This is what U48 does on the 256k 5150 board does. If A19 and or A18 are not a zero then the '138s that decide what bank is selected don't do anything.)

          A17 and A16: Again referencing the 5150 schematics, these are decoded by U47 and U65. These are set up to act as 1-in-4 decoders (see how half the outputs are "wasted"; looking at the IBM schematics it looks like IBM used them instead of '139s because they're relying on the multi-conditional output enable gates to add additional conditions beyond the address to gate the assertion of these signals) and which set of CAS/RAS signals is active, IE, which bank is enabled, is *directly based* on the state of A17 and A16. There's nothing more to do with them.

          To make your Sanyo access 256k in a bank you actually need to disconnect A16 and A17 directly from the CAS/RAS decoders (assuming that's how they're actually wired, that's why I said you need to figure out if there's a PROM, additional decoding, or *what* there) and instead generate a truth table something like this:

          (x = "don't care".)

          A19 A18 A17 A16 : Desired state
           0     0     x     x   : Enable RAS/CAS for bank 1 (256k, starting address 00000h)
           0     1     x     x   : Enable RAS/CAS for bank 2 (256k, starting address 40000h)
           1     0     0     0   : Enable RAS/CAS for bank 3 (64k, starting address 80000h)
           1     0     0     1   : Enable RAS/CAS for bank 4 (64k, starting address 90000h)
           All other states      : Nothing enabled.
          Note also that the first layer of decoding, U48 on the 5150, which is "active low" when *any* of the banks should be active, was also used as a control signal for several items, including a bidirectional '245 buffer in front of the RAM data lines, so whatever you do on the Sanyo to fix the RAS/CAS decoding also still needs to produce that total "memory is active, period" signal. So, again, it's A18 and A19 that you need to start decoding in more detail to get more than 256k, and that is where it matters critically how the Sanyo is doing it *now*.
          My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot


            Thank you. I'm sorry if I don't sound like I'm up to the task.
            There's a lot of jargon to sift through too, and I don't always get them right (despite my knowledge) and things lately haven't exactly been spring chicken.
            I do understand that there are lines that go from the CPU to memory. (Maybe not directly. Again, though, I tend to get them mixed up.)

            However, I've seen videos about how memory (Doom's cheat codes), and read about how disk contents [Apple II Disk II writing-to-disk methods], can be obfuscated, so I assumed that there was some shuffling/scrambling of groups of bits here and there to re-create the proper data grouping for the CPU to understand.

            The tracing of the pathways makes a bit more sense now.

            G, on [Sanyo] U45 and U47 is indeed attached to ground.

            Right now I'm reworking my pathway tracing to make it easier to read and organize. I'll see if I can look a bit more into the logic of the chips.
            Last edited by T-Squared; November 2, 2020, 08:58 PM.


              This mapping is already getting complex, but I'd like to see what I can do.

              I have noticed patterns that are cropping up:

              The 158s are all at least connected to an input (on one chip) AND an output (on another), forming a complex series of logic valves.
              Control pins (that control the impedence / basic on-off state) are all connected to GND.

              The good thing is that the RAS and CAS are indeed connected to 138s. Now I just need to figure out where those 138s figure into the picture.
              Last edited by T-Squared; November 5, 2020, 09:28 AM.


                A bit of progress today. I got my 64-kilobit chips in today, and I now have a full 640k of memory, which matches the amount in the 5160 schematics.
                I'm still mapping out connections, but it's slow because emotionally, I'm spent because of this quarantine.

                I'm betting that the logic connections don't match exactly with the IBM schematics; maybe what is the difference is that the connections are logically the same (same type of input pins, same type of output pins), but connected to different pin numbers because of routing differences in manufacturing?
                CuriousMarc did the same thing when performing repairs on a Xerox Alto. One logic gate within an IC was bad, so what he did was rerouted those signals to an unused gate of the same type on the other side of the chip, which allowed them to temporarily make progress until they could source a new modern-built version of the chip.


                  A bit of an update: looking at the schematics, this Sanyo is looking more and more like a 5160 clone. The components are all matching up in number and type to the schematics so far. I just need to find out what components are not connected properly.


                    Been a while. I got some UV EPROMS and burned a copy of the Supersoft Diagnostics. The diagnostic gets stuck at the 8253 Timer 1 check.

                    I get One Hi-Lo and 8 beeps. It suggests the 16k critical memory area is not working.
                    (Unless I'm misinterpreting, and the Hi-Lo means two beeps, in which case it says the numeric co-processor isn't working, but it seemed to work when I used the Landmark Diags about a month or two ago)
                    Last edited by T-Squared; December 4, 2020, 06:09 PM.


                      Ok, further investigation shows that the memory refresh is not occurring, due to Timer 1 not operating. I'll check it tomorrow and see if there's a wire that needs to be connected to the memory from there.


                        Sorry about the long wait. I had to wait for my diagnostic card to get in. I discovered something extremely odd. NOW the entire Supersoft Diagnostic runs, and it MAY be reading memory (not completely) somehow.

                        Anyways, I took out the two cards I had installed in the machine (A Western Digital 8/16 Ethernet Card and an XT-IDE CF card), and plugged in the diagnostics card. To my surprise, there was nothing frozen on the card's seven-segment LEDs. Even more strange, the screen now works properly, and it runs through the tests as normal. (Previously, with the diagnostic ROM, the picture would be unstable and roll, and it would stop at the Timer 1 test.)

                        I wonder if the previous cards had anything to do with it...
                        Attached Files


                          Yeah, this is weird. It's as if the problem with my computer is not how the memory is connected, but failing chips (Some of which I did get from China). It is reporting errors on memory banks, but not all of them. Some seem to actually be succeeding!

                          Would a real IBM not run if any memory chips in the 16K area were faulty?
                          Last edited by T-Squared; January 14, 2021, 12:59 PM.


                            I've forgotten... I'm actually getting the same consistent bit pattern errors across at least the first 256K of the upgraded RAM, and it's always in consistent address increments.
                            e.g. 2000h, 4000h, C000h, 12000h, 14000h... (Yes, I know that this is not correctly incremented. I'm trying to prove a quick point.)


                              Been a while. I'm still trying to figure out this stuff, but I think I've found analogous chips between the 5160 schematic and the Sanyo. And as expected and what has been said before, there is one 5160 chip on the schematic that does not exist on the Sanyo, replaced by the mess of logic chips, that performs the same functions, that I'm trying to organize.

                              I've been routing logic lines all week, looking for similarities as well, between the Sanyo and schematic.

                              The one thing I'm having problems with is trying to route the RAM Address select line on the Sanyo map I've drawn up, so I can figure out where the logical clone of this "decoder" chip starts. (as I inaccurately called it earlier.)


                                I thought I had something, but it's turned weird now.

                                I've heard of a jumper being added to a location on the normal 5160 board to get 640k to work, and the only other jumper available that was near the memory logic was a unpopulated one. (and it seemed suspicious because there was a resistor connected to one via of the through-hole pair, with another resistor behind it and a trace snaking off somewhere on the board.) So I added a pin header and a jumper to it.

                                I'm still having problems, and the reason why I said it was weird is because I took bank-after-bank of memory out to make sure the Supersoft diagnostic would detect that some of it was missing, but it's now reporting the wrong kind of error, which is what it did before: a memory failure at address 05040, with the same failing bits in memory (7,6,1, 0, or so), even though none exists on the board now.
                                Last edited by T-Squared; April 19, 2021, 06:07 PM.