prime
Experienced Member
Hi all,
Am I correct in assuming that only *ONE* of the the memory or I/O write strobes may be active at one time e.g. nMEMR, nMEMW, nIOR, nIOW ?
The reason I ask is because I have a RAM / Clock card (I have been developing on and off for a couple of years), this has an 74ALS245 buffer between the internal and external data lines.
The internal data lines have two AS6C4008 512Kx8 SRAM chips and a DS12887 RTC chip on them.
The logic for the chip enables and buffer enable/direction is controlled by an XC9572XL CPLD, this completely decodes the RAM and the RTC. The RTC I/O is only enabled if AEN is low.
So the buffer obviously need to be enabled when either the RAM or RTC is being accessed.
I'm having seemingly problems with switching the buffer direction, if I just use nMEMW everything works fine and the memory remains intact. If I switch on nIOW as well then it seems certain accesses to the clock will bork the RAM.
Cheers.
Phill.
Am I correct in assuming that only *ONE* of the the memory or I/O write strobes may be active at one time e.g. nMEMR, nMEMW, nIOR, nIOW ?
The reason I ask is because I have a RAM / Clock card (I have been developing on and off for a couple of years), this has an 74ALS245 buffer between the internal and external data lines.
The internal data lines have two AS6C4008 512Kx8 SRAM chips and a DS12887 RTC chip on them.
The logic for the chip enables and buffer enable/direction is controlled by an XC9572XL CPLD, this completely decodes the RAM and the RTC. The RTC I/O is only enabled if AEN is low.
So the buffer obviously need to be enabled when either the RAM or RTC is being accessed.
I'm having seemingly problems with switching the buffer direction, if I just use nMEMW everything works fine and the memory remains intact. If I switch on nIOW as well then it seems certain accesses to the clock will bork the RAM.
Cheers.
Phill.