pjh
Experienced Member
In recovering failed or erratically functioning S-100 boards, one of the things
that I do is chip test as many of the 74xx TTL chips that I can. I use a breadboard
set up with a 555 timer and a 7493 4-bit binary counter to provide input signals for
the chips to be tested. On chips with more that 4 inputs, I pair up the inputs so
that the whole chip can be tested at one time. One thing I have noticed over time
is a high failure rate of the 74LS30 chip, even on orders of new chips from suppliers.
First, let me define 'failure' as I see it in this case. Perhaps someone can
tell me if these are in fact failures. In my testing I check first to make sure that
any chip is functioning as it is designed, and then I watch for clean HIGH-LOW
transitions in the outputs of the chips. The 74LS30, an 8-input positive-nand gate,
seems to 'fail' often in that the output doesn't do a clean HIGH-LOW transition but
instead does a HIGH-DIM-LOW transition. I have been assuming that a HIGH-DIM-LOW
transition in any chip would produce an invalid logic state in a circuit for the period
of time that the DIM state exists. So, I replace the chips that produce these results
as well as any obviously bad chips.
I find these 'failing' 74LS30 chips often on boards that I am chip testing but I
also find that in orders of 74LS30 chips, many of them are also 'failing'. I may
get as many as half or more of the chips I have ordered to produce this HIGH-DIM-LOW
output. Other chips such as the 74LS240 or 74LS244 may show the HIGH-DIM-LOW
transitions as they begin to fail but I rarely see such HIGH-DIM-LOW outputs on
orders of any other new chips. Has anyone else seen such a high failure rate in
74LS30 chips?
Phillip
that I do is chip test as many of the 74xx TTL chips that I can. I use a breadboard
set up with a 555 timer and a 7493 4-bit binary counter to provide input signals for
the chips to be tested. On chips with more that 4 inputs, I pair up the inputs so
that the whole chip can be tested at one time. One thing I have noticed over time
is a high failure rate of the 74LS30 chip, even on orders of new chips from suppliers.
First, let me define 'failure' as I see it in this case. Perhaps someone can
tell me if these are in fact failures. In my testing I check first to make sure that
any chip is functioning as it is designed, and then I watch for clean HIGH-LOW
transitions in the outputs of the chips. The 74LS30, an 8-input positive-nand gate,
seems to 'fail' often in that the output doesn't do a clean HIGH-LOW transition but
instead does a HIGH-DIM-LOW transition. I have been assuming that a HIGH-DIM-LOW
transition in any chip would produce an invalid logic state in a circuit for the period
of time that the DIM state exists. So, I replace the chips that produce these results
as well as any obviously bad chips.
I find these 'failing' 74LS30 chips often on boards that I am chip testing but I
also find that in orders of 74LS30 chips, many of them are also 'failing'. I may
get as many as half or more of the chips I have ordered to produce this HIGH-DIM-LOW
output. Other chips such as the 74LS240 or 74LS244 may show the HIGH-DIM-LOW
transitions as they begin to fail but I rarely see such HIGH-DIM-LOW outputs on
orders of any other new chips. Has anyone else seen such a high failure rate in
74LS30 chips?
Phillip