Hugo Holden
Veteran Member
I am working with a Matrox ALT 512 graphics card to make a light pen project. I have figured out how to write to the card with programs and image files etc. I figured it wouldn't be much use with the light pen, unless I could save the file that was in the Matrox Ram. So for the first time I attempted to interrogate the ports of the card and save the video bit. This is where an interesting anomaly cropped up, but it might be something that is plainly obvious to an experienced graphics card programmer:
The 512 manual says:
"Reading from port 0 will execute a refresh memory read cycle. The video bit addresses by content of of X,Y and the plane register is read at DO. (data line output 0 in pin 95 of the card).
Elsewhere it remarks: Synchronization of the TV scan and the CPU read-write and clear is done by flip flops A8 and A9. (checked and appear to be working)
This sort of suggested that there is a form of synchronization at least to acquire and write data to the card, so the CPU does it at the right time. Also it occurred to me that the reads would have to avoid the times when the RAMs were being refreshed. It is obvious that outside the H and V blanking times the RAM data is stable, as it appears on the Monitor's image.
However, a short loop in BASIC, with the X and Y registers programmed for an ON pixel location:
10 PRINT INP(0);
20 GOTO 10
30 END
when run prints correctly 255, most of the time, however prints at intervals the occasional value of 254 which is incorrect.
Going over the card with the scope, I could not find any defect and the synchronization circuit appears to be working, I think, except for this:
The scope analysis shows that the CPU does attempt to do a read at times within the H an V blanking periods. The CPU timing and the card's video generator timing are of course not phase locked in any way and are crawling with respect to each other. I think what is happening is the CPU is attempting to acquire data from the video RAM at a moment were they are being refreshed, hence occasionally corrupting the acquired video bit value.
It suggests that the software should be written to check the H and or V blanking flags (there is a register for those) and not attempt to read the video bit inside the blanking time. Would that kind of thing be standard practice for reading a video card's memory, or is it not supposed to matter and be handled at the hardware level ?
(In other words I'm not sure if the card might have a hardware issue or not)
The 512 manual says:
"Reading from port 0 will execute a refresh memory read cycle. The video bit addresses by content of of X,Y and the plane register is read at DO. (data line output 0 in pin 95 of the card).
Elsewhere it remarks: Synchronization of the TV scan and the CPU read-write and clear is done by flip flops A8 and A9. (checked and appear to be working)
This sort of suggested that there is a form of synchronization at least to acquire and write data to the card, so the CPU does it at the right time. Also it occurred to me that the reads would have to avoid the times when the RAMs were being refreshed. It is obvious that outside the H and V blanking times the RAM data is stable, as it appears on the Monitor's image.
However, a short loop in BASIC, with the X and Y registers programmed for an ON pixel location:
10 PRINT INP(0);
20 GOTO 10
30 END
when run prints correctly 255, most of the time, however prints at intervals the occasional value of 254 which is incorrect.
Going over the card with the scope, I could not find any defect and the synchronization circuit appears to be working, I think, except for this:
The scope analysis shows that the CPU does attempt to do a read at times within the H an V blanking periods. The CPU timing and the card's video generator timing are of course not phase locked in any way and are crawling with respect to each other. I think what is happening is the CPU is attempting to acquire data from the video RAM at a moment were they are being refreshed, hence occasionally corrupting the acquired video bit value.
It suggests that the software should be written to check the H and or V blanking flags (there is a register for those) and not attempt to read the video bit inside the blanking time. Would that kind of thing be standard practice for reading a video card's memory, or is it not supposed to matter and be handled at the hardware level ?
(In other words I'm not sure if the card might have a hardware issue or not)