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I wish to create a new DMA/RAM expansion card for the Tandy 1000 line.

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    Originally posted by eeguru View Post
    If you are using two 512K chips with a 1:1 mapping of chip ram to physical memory space, and are ok with throwing away conflicting RAM, what you propose is fine.
    I think I've actually worked out a way to use the remaining 128k left over from the base memory backfill for UMBs in D and E, but the granularity is only 64k. The logic is embodied in the sandbox link I threw out earlier. Essentially it boils down to this:

    1: the RAM chip is on A0-18. It has no idea about A19 so you can pack it with ranges from both ends of memory as long as they don't result in overlapping addresses.

    2: The 'E' page is easy because it's the first half of the unused 128k, just need a chip select. (That's where the '138 comes in. I can't offhandedly think of a better solution without programmable logic.)

    3. For D000h, normally that would be a no-go because that results in the same address line formula on the sram as the 5000h page. However, I tinkered together a way using leftover gates from the AND and NANDs I already need to selectively invert the A17 line that's routed to the RAM when the D chip select is active. That effectively moves the D page after the E page, bingo, full utilization.

    I posted a truth table earlier, assuming I wasn't completely walleyed when I transcribed it I think it should work. A slightly confusing side effect of the particular combination of gates is actually A17 is inverted *except* when the D-select is active, so physically every other 128k boundary is flipped, but the computer won't care.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

    Comment


      Use Logic Friday. It will even optimize the circuit by chip count.
      "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

      Comment


        Originally posted by eeguru View Post
        Use Logic Friday. It will even optimize the circuit by chip count.
        I'm fiddling with Logic Friday now; does it support mapping to anything other than standard stand-alone gates like NANDs/NORs/ANDs/etc? Unless it's hidden somewhere it doesn't have the option of using built-up decoders like a 138/139. The best I can come up with using it still requires three ICs for the base/UMB mapping. Granted it's sort of impressive that it can minimize that down to three using just plain gates.

        For my board, though, I want a separate Cxxx enable for the flash. There doesn't seem to be any solution in Logic Friday that can do that with less than four. Using a '138 for the top decoding gives me that with three packages. (Technically it wastes a bunch of gates inside the '138, of course.)

        It's still a nifty tool, though, and I'll definitely use it.
        My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

        Comment


          Doesn't appear there is an option for mux parts. I do like the visualization option for tracing logic through the generated circuit.
          "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

          Comment


            FWIW, I found another old Windows program that might be useful for working with discrete 7400 series logic. It's called "Atanua":

            https://sol.gfxile.net/atanua/

            It has a library of 74xx logic you can drop on a canvas, draw lines between according to your schematic, and check conditions by setting input switches.

            logic.jpg

            (The 7404 in the screenshot isn't actually part of the circuit from my latest schematic, I put it in to make a slightly-more-user-friendly display of some intermediate conditions; chip selects are active low, of course, but it's easier for most mere mortals to think a lit light means "on". It's basically a logic probe.)

            Also finished routing a board that uses the addressing schema I've now tested in Atanua. I decided to go ahead and include the three row Plus connector layout on this one. Might still use the stacking headers for a prototype but it gives the option to do the Plus offset method. I crammed it all onto a 100x100mm cheap-prototype-sized board so it doesn't have the standard mounting holes for a backplate or anything.

            Tandy-RAM-Flash-clock-UMB.jpg
            Last edited by Eudimorphodon; June 23, 2019, 02:06 PM.
            My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

            Comment


              Originally posted by blackepyon View Post
              I've got scribbled in my notes that the SmartWatch resides at E0000h (that would be A17,A18,A19 high), but that doesn't make sense, because the BIOS ROM only uses A00-A16, residing at F200h. I don't remember where I saw it originally. Might be the SmartWatch utility itself that says that, but as my original died, I can't confirm why I have this written down... Unless it was supposed to be E000h and I accidentally added an extra 0? That would be A13, A14, A15 high.
              The Tandy smartwatches (and the DS no-slot clocks) are parasitic on existing chip selects, so its base address would be whatever the address of the socket you've got it plugged into is.

              Also, don't forget this about address lines: All memory devices are typically going to have A0-Asomething-less-than-the-available-address-space. A ROM that has up to A16 would have 128k's worth of addresses in it, so when interfacing to a machine with 20 address lines it's up to the decoding hardware in the computer to handle A17-19. So in this theoretical case a ROM mapped at the E-page to end of memory would need some external decoder that would enable it when the state of the highest three address lines are "111".

              Re: extra zeros, I've been fighting confusion about the convention in the 8086 world to us, say, "E000h" to refer to the physical address space that corresponds with E0000 hex on the address bus instead of using all the zeros. I *believe* the reason why is because when they drop the last zero they're referring to the most straightforward way of setting the segment portion of the segment/offset combination that the CPU can be programmed with to refer to that physical location, but I'm extremely rusty on the details. (I know on the 8086 there are literally thousands of combinations of segment/offset that point to the same physical address.)
              My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

              Comment


                Originally posted by blackepyon View Post
                I've got scribbled in my notes that the SmartWatch resides at E0000h (that would be A17,A18,A19 high), but that doesn't make sense, because the BIOS ROM only uses A00-A16, residing at F200h. I don't remember where I saw it originally. Might be the SmartWatch utility itself that says that, but as my original died, I can't confirm why I have this written down... Unless it was supposed to be E000h and I accidentally added an extra 0? That would be A13, A14, A15 high.

                dJOS, do you remember what it was supposed to be?
                My understanding is the "SmartWatch" chip must be installed with a ROM chip that responds to memory accesses at F000:000 for the software to recognize it.

                EDIT: the SMWCLK software does a sweep search - here's the ASM code for the Y2K patched version:

                https://www.dropbox.com/s/6gxaknvm5v...CLOCK.ASM?dl=0
                Last edited by dJOS; June 23, 2019, 03:26 PM.
                My Retro Collection:
                CBM: C64, Amiga 500 x2, 600 & 1200
                Apple's: IIc, Mac SE, LCII, LC630 & Power Mac G3/233 Desktop
                PC's: K6-III+ 500 System + Roland MT-32 & Tandy 1000 EX 640kb, 3.5" FDD, CF-IDE 4GB HDD
                Visit my Tindie store for Tandy 1000 Adapters for EX, HX, SX, SL, TX & TL etc

                Comment


                  Originally posted by dJOS View Post
                  My understanding is the "SmartWatch" chip must be installed with a ROM chip that responds to memory accesses at F000:000 for the software to recognize it.

                  EDIT: the SMWCLK software does a sweep search - here's the ASM code for the Y2K patched version:

                  https://www.dropbox.com/s/6gxaknvm5v...CLOCK.ASM?dl=0
                  Code:
                  ;----------------------------------------------------------------------;
                  ;                                                                      ;
                  ;                                                                      ;
                  ;       SmartWatch search routine                                      ;
                  ;                                                                      ;
                  ;                                                                      ;
                  ;----------------------------------------------------------------------;
                  ;       This routine searches for a SmartWatch in the address space    ;
                  ;       of the PC by performing the following series of actions:       ;
                  ;                                                                      ;
                  ;               - Initialize segment search at ^xC000, increment 64kb  ;
                  ;               - Read watch using test segment                        ;
                  ;               - If data read is invalid, then reselect               ;
                  ;                 segment using an updated segment value.              ;
                  ;                                                                      ;
                  ;       Invalid watch data is determined via the following criterion:  ;
                  ;                                                                      ;
                  ;               - data of all 1s is invalid                            ;
                  ;               - data of 1s in must-be-zero (MBZ) areas is invalid    ;
                  ;                                                                      ;
                  ;       A second level of testing is also performed in the event that  ;
                  ;       the returned data meets the above criterion.  This involves    ;
                  ;       rewriting the year field with a test pattern and then reading  ;
                  ;       back the result.  If this can be done with a variety of data   ;
                  ;       patterns, then the SmartWatch has in fact been located.        ;
                  ;----------------------------------------------------------------------;
                  ;       Arguments:      SW$PARA contains the memory segment in which   ;
                  ;                               the SmartWatch is positioned           ;
                  ;                               (set by this routine)                  ;
                  ;                       SW$TIME returns the current SmartWatch time    ;
                  ;----------------------------------------------------------------------;
                  ;                                                                      ;
                  ;       Initialize new increment and segment search                    ;
                  ;                                                                      ;
                  ;----------------------------------------------------------------------;
                  SEARCH: MOV     DX,01000h               ; Initialize search increment (64kb)
                  ADDRESS:MOV     SW$PARA,0C000h          ; Initialize search segment
                  MODE:   MOV     SW$MODE,3               ; Initialize access mode
                  I am in no way conversant in Assembler. Does this mean that it starts the search at C000h and moves on in 1000h steps if it doesn't get the return it's looking for?
                  My vintage systems: Tandy 1000 HX, Tandy 1000 RSX, Tandy 1100FD, Tandy 64K CoCo 2, Commodore VIC-20, Hyundai Super16TE (XT clone), and some random Pentium in a Hewitt Rand chassis...

                  Some people keep a classic car in their garage. Some people keep vintage computers. The latter hobby is cheaper, and is less likely to lead to a fatal accident.

                  Comment


                    re: your board rendering, the centre header should be the male header facing down to the motherboard. There's only two slots available with the memory board installed.

                    Originally posted by Eudimorphodon View Post
                    The Tandy smartwatches (and the DS no-slot clocks) are parasitic on existing chip selects, so its base address would be whatever the address of the socket you've got it plugged into is.

                    Also, don't forget this about address lines: All memory devices are typically going to have A0-Asomething-less-than-the-available-address-space. A ROM that has up to A16 would have 128k's worth of addresses in it, so when interfacing to a machine with 20 address lines it's up to the decoding hardware in the computer to handle A17-19. So in this theoretical case a ROM mapped at the E-page to end of memory would need some external decoder that would enable it when the state of the highest three address lines are "111".
                    That makes sense. The ROM at U12 is getting it's *CS from U16, which is a PLA that has A16-A19 feeding into it. E000h onwards to FFFFh (end of mapped memory in this short-hand notation) are contained on that ROM. It ought to be E0000h to FFFFFh in long-hand, which gives the correct size of that ROM (128Kbx8 = 128KB).

                    That's on the HX anyways. On the EX, it's a 32KB ROM at U17 (no DOS in ROM), with the PLA at U3. That would put the EX's ROM at F7FF(F), I think, if they've got it at the end of the memory map?

                    Re: extra zeros, I've been fighting confusion about the convention in the 8086 world to us, say, "E000h" to refer to the physical address space that corresponds with E0000 hex on the address bus instead of using all the zeros. I *believe* the reason why is because when they drop the last zero they're referring to the most straightforward way of setting the segment portion of the segment/offset combination that the CPU can be programmed with to refer to that physical location, but I'm extremely rusty on the details. (I know on the 8086 there are literally thousands of combinations of segment/offset that point to the same physical address.)
                    The "short-hand" is especially confusing, since you end up overlapping with I/O addresses. Further confusing is that Checkit's printout gives the memory map without that extra digit. I think it's better to just assume that I/O is going to be 4 hex-digits long, and memory address 5 hex-digits long, and every schematic I've looked up using '688s for address selection bear this out.

                    Very convenient that Windows' calculator has "programmer mode." Makes calculating addresses SOOOO much easier, cause you can see directly which address pins are involved, and there's even a tab where you can toggle individual bits on and off for working out your jumper settings.
                    My vintage systems: Tandy 1000 HX, Tandy 1000 RSX, Tandy 1100FD, Tandy 64K CoCo 2, Commodore VIC-20, Hyundai Super16TE (XT clone), and some random Pentium in a Hewitt Rand chassis...

                    Some people keep a classic car in their garage. Some people keep vintage computers. The latter hobby is cheaper, and is less likely to lead to a fatal accident.

                    Comment


                      Originally posted by blackepyon View Post
                      re: your board rendering, the centre header should be the male header facing down to the motherboard. There's only two slots available with the memory board installed.
                      Yeah, I know. All three banks of holes have the same header gender and orientation in the render because I didn't want to bother making a separate flipped version of the Tandy Plus symbol footprint for the down-facing connector. When assembling a real board I'd of course solder it appropriately.
                      My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                      Comment


                        Originally posted by Eudimorphodon View Post
                        Yeah, I know. All three banks of holes have the same header gender and orientation in the render because I didn't want to bother making a separate flipped version of the Tandy Plus symbol footprint for the down-facing connector. When assembling a real board I'd of course solder it appropriately.
                        Assuming you're using Ki-Cad: Footprint = "Connector_PinSocket_2.54mm:PinSocket_2x31_P2.54mm _Vertical"
                        Just flip the component.
                        My vintage systems: Tandy 1000 HX, Tandy 1000 RSX, Tandy 1100FD, Tandy 64K CoCo 2, Commodore VIC-20, Hyundai Super16TE (XT clone), and some random Pentium in a Hewitt Rand chassis...

                        Some people keep a classic car in their garage. Some people keep vintage computers. The latter hobby is cheaper, and is less likely to lead to a fatal accident.

                        Comment


                          So:

                          I created a custom Tandy Bus library symbol with all the signals labeled (Based on a clone of the ISA slot library object that comes with Kicad) and it goes with a footprint that's a version of the header connector that has pin assignments that match the ones Tandy used. (IE, row a/b 1-31 instead of the standard even-odd stagger.) The point of view for the physical mapping is looking down at the male connector, because that's most intuitive when you're putting together a schematic. (And it was also my plan to use stacking headers; the orientation makes sense for those too.) If I flip that in PCBnew of course the rows will be backwards because it's going to assume the same orientation applies, so if I really care about making the rendering exact I'll need a second version of the footprint with the mirrored orientation to go along with the flipped position. (And of course associated with the socket instead of the header.)

                          If I'd known it'd be such a hassle with the pin-mapping of symbols to footprints I would have probably used standard odd-even numbers instead of the making the pin assignments match on my symbol. An annoying inconsistency in Kicad seems to be that it has defined *symbols* for Ax/Bx numbering but not footprints. IE, in the schematics generator you can select a symbol for a "Connector_Generic" with row-letter numbering, I used that for the "pass-through" connectors on the schematic, but unless there's a button I'm missing you're screwed when you do that because the header pin *footprints* for pin socket/headers are even-odd; if I select that pinsocket and associate it the ratsnest is broken because it doesn't automatically transcribe the pin assignments. Therefore I ended up assigning the custom footprint I made for the Tandy Bus symbol with the row/letter passive connectors too.

                          (If there really is a button for patching up the pin-row misalignments automatically that I just keep missing I'd love to know where it is.)

                          I think I'd care more about this detail if it wasn't for the generated gerbers looking to me like boards have the same size solder pad area on both sides, therefore making it not matter for soldering the physical connector if I just use the same array for all three.
                          Last edited by Eudimorphodon; June 24, 2019, 10:32 AM.
                          My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                          Comment


                            Originally posted by blackepyon View Post
                            That's on the HX anyways. On the EX, it's a 32KB ROM at U17 (no DOS in ROM), with the PLA at U3. That would put the EX's ROM at F7FF(F), I think, if they've got it at the end of the memory map?
                            Looking at the EX's tech manual it looks like it might only have 16k of ROM, starting at F0000h. (The parts list says it has a "128k ROM" they appear to mean a 128Kbit, not byte, ROM. The schematic, however, shows the socket wired for up to a 32k ROM, so even if only 16K is actually used it probably repeats in the memory map.) I believe generic PCs usually have the last half of the F-page open because that's where original IBMs stuck the Cassette Basic ROM, but there's nothing saying that a particular clone couldn't use it for something else. A peek at the HX's manual confirms that in its case the socket is indeed wired for 128k's worth of addresses.

                            The interesting thing about how those Smartwatches work is because they only listen to A0 and A2 for the magic pattern they technically live throughout the entirety of the ROM's address space and could be accessed from any point inside it. If the HX ROM does indeed start at E000h because that's where the DOS portion lives then presumably that's where a detection routine starting from the bottom up looking for a smartwatch would find it.
                            My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                            Comment


                              Originally posted by Eudimorphodon View Post
                              So:

                              (excuses for not caring about the render)
                              I just went ahead and made a female socket footprint for the flipped orientation. New render, including silkscreen for what the jumpers do:

                              Tandy-RAM-Flash-clock-UMB-2.jpg

                              Even though I'm still missing a few of my "from china" orders I'm thinking of sending this off to a PCB mill for a $5 prototype at this point. I have enough parts on hand to populate the decoders, buffer, and RAM portions of the circuitry. (Minus the female connector for the bottom if I don't use the stacking headers, grrrr...)
                              Last edited by Eudimorphodon; June 24, 2019, 12:59 PM.
                              My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs Also: Blogspot

                              Comment


                                On the HX at least (can't speak for the EX), the system ROM starts at FC000h and is not aliased in the F segment. There is an option ROM from F0000h to F0200h with the 95 sector DOS-in-ROM 'floppy' image from F0200h to FC000h. The option ROM installs an Int 13h handler for the ROM disk. There is code and data in the E segment. But as far as I could tell (based on string data) when I deep dove into it a couple years ago, that is part of a resident portion of DeskMate 2 that isn't loaded from floppies.
                                "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

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