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8086 Based Computer Design

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    8086 Based Computer Design

    This thread is to discuss GOLD CHIP idea of building a 8086 based computer.

    Last post by GOLD CHIP:
    It gives me time to think it over thoroughly.

    I want this project clean and pure 16-bit design. to do with that I need to get away from "IBM PC compatibility". Hmmm why can't I think of that many years ago. stupid me.

    ok.

    the spec. would be

    1. clean 16-bit design
    2. using 8086 micro (not FPGA clone hehe) // allready have 2 tube of 8086 chips.
    3. using 16-bit SRAM (I allready have the 16-bit SRAM chip)
    4. all those glue logic would be in FPGA.

    Question
    how do we design the easiest DMA, PIC, PIT, keyboard controller (using PS2 keyboard)?

    My guess is to design the address for each DMA, PIC, etc. and then call the FPGA guy to do the rest.

    Question again:
    How do we modified the BIOS to suit this new arrangement of glue chips.

    Thank you in advance

    #2
    I don't see how one can practically get beyond the need of an MCU for PS/2 keyboard interfacing.

    If PC compatibility isn't important, why not an 80186/V50 with the peripheral interfacing already taken care of? Heck, the 186 even has programmable chip selects and is perfectly contemporaneous with the IBM 5150.

    Comment


      #3
      I'd vote for the 80186 as well, preferably in a PLCC package. You could still socket it and retain a through-hole design.
      Check out The Glitch Works | My Retro Projects | Vintage Computer Services | Glitch Works Tindie Store -- Vintage Computer Kits and More

      Comment


        #4
        GOLD CHIP,

        You need to decide on and describe the goals of your project in more detail. If you're going pure 16-bit (non-IBM PC compatible) route, both hardware and software doesn't have to match the IBM PC implementation.
        Some examples:
        - Extension bus to be used. Some choices: ISA (be aware that not all cards will work with "pure 16-bit", even not all 16-bit cards), S-100, ECB...
        - DMA in IBM PC is implemented in a very hackish fashion. The DMA chip itself (8237) was not intended to be used with 8086/8088 and doesn't support 20-bit address and can only generate 16-bit address. It also doesn't integrate well with 8086/8088 configured in maximum mode. The IBM PC uses "fake" wait states to grab the bus for DMA. First question here - do you need DMA at all? Some popular devices that use DMA are: Floppy disk controller, Sound cards (for digitized samples playback), some hard drive controllers. Floppy disk controllers can also work without DMA, and it is not very likely that you'll have an old XT hard drive controller than needs DMA. So only sound cards left... If you think you still need DMA, you might check for alternatives (although they can be difficult to find at this point of time).
        - PIT in IBM PC one channel is used for memory refresh, you don't need it since you will be using SRAM. You can re-purpose it. (In Xi 8088 I connected the channel 0 to a FF. FF output toggles with every timer pulse, and its output that can be read through port 61h. This is very similar to what AT is doing, and it can used for timing purposes, e.g. delays)
        - 8259 PICs are probably OK... the question is how many PICs do you want. One provides 8 interrupts, it is possible to cascade them and have up to 256 interrupts. AT cascades two PICs (and so Xi 8088 ), so it has 15 interrupts... (7 on master PIC and 8 on slave PIC).
        - Keyboard is a relatively simple part. I have three options: 1) Use VT82C42 or any other AT or PS/2 compatible keyboard controller. 2) Use a Propeller chip with a corresponding firmware. It can also handle other things (VGA output, SD card interface) for example refer to this project. 3) Implement a simple serial interface (similar to the PC/XT one) in CPLD or using discrete logic, and use AT2XT converter to connect an AT or PS/2 keyboard. You can implement the AT2XT functionality on your board (it is just a simple PIC micro).
        - On software side, regardless of the type of IBM-compatible BIOS your choose, it will need to be extensively modified to match the system hardware. (By the way what is the target OS?)
        Last edited by sergey; March 7, 2013, 11:37 AM.

        Comment


          #5
          Originally posted by Chuck(G) View Post
          I don't see how one can practically get beyond the need of an MCU for PS/2 keyboard interfacing.

          If PC compatibility isn't important, why not an 80186/V50 with the peripheral interfacing already taken care of? Heck, the 186 even has programmable chip selects and is perfectly contemporaneous with the IBM 5150.
          I'm considering 80186, I've studied the datasheet of it in detail. BUt I'm inclined to using 8086 since I allready have 2 tube of them. Lemme think

          Comment


            #6
            Originally posted by GOLD CHIP View Post
            I'm considering 80186, I've studied the datasheet of it in detail. BUt I'm inclined to using 8086 since I allready have 2 tube of them. Lemme think
            Be sure to check out all of the variations--the 186 isn't a single chip, but rather a family of them that comes in anything from a 68 pin PLCC to 144 pin QFP.

            Comment


              #7
              Originally posted by sergey View Post
              4. all those glue logic would be in FPGA.
              I don't understand this temptation. If you really mean FPGA as a traditionally larger part, the rabbit hole can get pretty deep as there are already numerous system level designs in soft-IP for everything from the DMA controller, clock chip, bus mux, keyboard controller, even VGA controller to the extreme of a soft 8086 CPU core itself. And you also have to deal with 3.3V interfacing. If you mean smaller CPLDs and SPLDs like using a +5V 22V10 or ATF1504 in places to cut the gross chip count down, a nifty little board could be built. But not as nifty as using a more integrated CPU if DOS/IBM compatibility isn't a design goal.

              A 4-12 SMP 8086 with a significant bit of PLD glue to provide HW spin locks and shared memory mapping would be a thought tickling project however.
              "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

              Comment


                #8
                Originally posted by eeguru View Post
                A 4-12 SMP 8086 with a significant bit of PLD glue to provide HW spin locks and shared memory mapping would be a thought tickling project however.
                There you go

                Make it an 8086-based supercomputer, the way Intel originally meant it to be. Use 8289 bus arbiters, put some 8089 for I/O acceleration instead of DMA.

                See this for a rough description of multiprocessor 8086 system: http://pimlico.phys.appstate.edu/phy...processors.pdf

                Comment


                  #9
                  Run iRMX on it too and use a Multibus backplane.

                  The 8086 was a "stopgap" product and probably persisted only because Intel couldn't make a go of the 432.

                  Comment


                    #10
                    Originally posted by Chuck(G) View Post
                    Run iRMX on it too and use a Multibus backplane.

                    The 8086 was a "stopgap" product and probably persisted only because Intel couldn't make a go of the 432.
                    I was thinking about using small RTOS which usually used in low_end mobile phone. I find the word "mobile phone" is attention grabber for student, instead of "computer architecture".

                    Could you tell me more about the "stopgap" and 432 stories?

                    Comment


                      #11
                      Originally posted by sergey View Post
                      There you go

                      Make it an 8086-based supercomputer, the way Intel originally meant it to be. Use 8289 bus arbiters, put some 8089 for I/O acceleration instead of DMA.

                      See this for a rough description of multiprocessor 8086 system: http://pimlico.phys.appstate.edu/phy...processors.pdf
                      very interesting, have anyone ever built this. I'd like to have a video of it running in its full capacity.
                      BTW I've never read 8089 datasheet, so I have to attuned my brain to it.

                      Comment


                        #12
                        Originally posted by eeguru View Post
                        I don't understand this temptation. If you really mean FPGA as a traditionally larger part, the rabbit hole can get pretty deep as there are already numerous system level designs in soft-IP for everything from the DMA controller, clock chip, bus mux, keyboard controller, even VGA controller to the extreme of a soft 8086 CPU core itself. And you also have to deal with 3.3V interfacing. If you mean smaller CPLDs and SPLDs like using a +5V 22V10 or ATF1504 in places to cut the gross chip count down, a nifty little board could be built. But not as nifty as using a more integrated CPU if DOS/IBM compatibility isn't a design goal.

                        A 4-12 SMP 8086 with a significant bit of PLD glue to provide HW spin locks and shared memory mapping would be a thought tickling project however.
                        definitely not 3.3V. I just want to have all the glue logic in one big chip, preferably DIP.

                        Comment


                          #13
                          Originally posted by GOLD CHIP View Post
                          definitely not 3.3V. I just want to have all the glue logic in one big chip, preferably DIP.
                          Err Glue logic also defines the term address decoding which traditionally used 74 logic components.
                          Let's say you want to have simple slabs of 128KB you could use a single 74138 to divide the address space in that manner which is rather wastefull IMHO.

                          Let's keep it simple and straight forward and use combinational logic to decode the address for chip select in addition to the formentioned 74138.

                          Comment


                            #14
                            I'm dead certain that Intel published a few reference designs for this. Wasn't iRMX supposedly multi-processor capable?

                            There's still plenty of 5V CPLD stuff around, so don't rule out programmable logic.

                            Comment


                              #15
                              Originally posted by Chuck(G) View Post
                              I'm dead certain that Intel published a few reference designs for this. Wasn't iRMX supposedly multi-processor capable?

                              There's still plenty of 5V CPLD stuff around, so don't rule out programmable logic.
                              CPLD would be ATF2500C

                              BTW, could you explain how 8086 can address 2Mbyte of RAM. thanks

                              Comment

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