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Sol-20 vertical sync pulse non-standard

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    Sol-20 vertical sync pulse non-standard

    I thought I would post this observation in case anyone else had the same issue.

    I noticed recently trying some different video monitors on my SOL-20 (Monitor from the IBM5155 computer) that there was a horizontal timing disturbance at the start of scan after the vertical interval, causing a horizontal timing irregularity in the position of text characters at the top of the screen. So I investigated it. See attached images.

    It turned out that the sync separator in the video monitor was malfunctioning, because the SOL-20 was delivering a vertical sync pulse of around 760 to 800 uS long (when it should be around 190us or about three H periods). It was easy to modify the monitor's sync separator by changing a resistor value so it could work with the wider vertical sync pulse. However, this monitor when fed by a standard signal (as it receives say in the 5155 computer from its CGA card) the sync separator of course behaves perfectly normally as one would expect.

    On inspecting the SOL's circuitry, I was surprised to find that the vertical sync pulse width is not generated digitally, but by a pseudo one shot composed of a cmos gate, capacitor , resistor and diode. By lowering the resistor value there below its current value of 100k, this shortens the vertical sync pulse width and it can be made to be close to standard.

    However, this problem will only show in up practice if the particular TV or video monitor connected to the SOL has a sync separator design where it is upset by the abnormally long vertical sync pulse from the SOL. Probably all SOL's are like this, the timing components (100k resistor and 0.01uF capacitor) appear to be within spec. But it would be good if this was checked on another SOL just in case the problem is unique to mine.

    The easiest fix is to simply reduce the 100k resistor value in the SOL, but in my case I left the SOL as it was, and changed a resistor in the monitor instead.
    Attached Files

    #2
    Good to know - thanks!

    Mike

    Comment


      #3
      Mike,

      If you get a chance sometime, can you check the video output on the scope on one of your Sols to see if the vertical sync pulse width is the same as mine or close ? In theory, if the RC network is in spec, the exact delay would only then be affected by the particular Cmos logic gate's input thresholds.

      Hugo.

      Comment


        #4
        Also Mike, the odd thing about this is that PT went to a lot of trouble it appears so as to get the timer for the H sync width correct, at practically exactly 5uS. But the vertical sync is way too long. For example experiment shows that the 100k resistor they have there, it would need to be changed to 25k to get the V sync pulse width to standard which is about 3H periods or 190 uS long. So their resistor value is "off" by a factor of 4 which seems very strange. Also one would expect it to have a time constant of 0.7RC( because of the gate threshold at 50% supply rail), so it is giving what the calculations suggest.

        Comment


          #5
          Interesting exercise...

          I took a look at the video output on my Sol-20 and I have no vertical sync encoded at all! This explains why my video has always rolled so easily if my monitor’s vertical adjustment is not in a perfect sweet spot. The clamp diode in the vertical sync pulse circuit (D9) has failed, so that circuit is acting like a switched capacitor voltage doubler and it’s generating 10v peaks. I’ll replace D9 and then see if the 4049 is still OK.

          I see the timing spec on the vertical pulse out of the 4049 is designed to be 600us (see page III-21 in the Sol-20 manual), so what you’re seeing is indeed their intended design.

          Mike

          Comment


            #6
            This just gets more interesting. I replaced D9 and I now have a vertical sync output similar to your original measurements - mine is about 650us. But, now that I have vertical sync, the 9Ē Panasonic CCTV monitor Iíve always used with my Sol-20 has a problem with the top few lines of the raster like youíre experiencing...

            Using clip leads I added 100K in parallel with the 100K on the board and the monitor is happy now. This reduces the vertical sync pulse to about 350us. Iíll have to decide what I want to do about fixing it permanently.

            Mike

            Comment


              #7
              Originally posted by deramp5113 View Post
              Interesting exercise...

              I took a look at the video output on my Sol-20 and I have no vertical sync encoded at all! This explains why my video has always rolled so easily if my monitor’s vertical adjustment is not in a perfect sweet spot. The clamp diode in the vertical sync pulse circuit (D9) has failed, so that circuit is acting like a switched capacitor voltage doubler and it’s generating 10v peaks. I’ll replace D9 and then see if the 4049 is still OK.

              I see the timing spec on the vertical pulse out of the 4049 is designed to be 600us (see page III-21 in the Sol-20 manual), so what you’re seeing is indeed their intended design.

              Mike
              That is interesting, what a thing to find, no v sync !

              I didn't find that spec the manual , I was looking in the wrong section !

              So now we know PT did it deliberately and the 750 to 800uS in mine is probably in the range of component tolerance for this type of circuit.

              It is odd they went for a non standard V sync pulse width, especially since the Sol's were designed to either pass their video to a standard video monitor or to a TV modified for video injection, or possibly with an RF modulator. All TV's and most video monitors of the time in the USA were expecting to see a vertical sync pulse of about 3 x 63.5uS or 190uS long. But not all of course would get that twist in the video at the top, it depends on the exact sync separator design. For example I have a Panasonic monitor that doesn't mind the longer vertical pulse at all.

              I think the best move is to place a resistor in parallel with the 100k until the V pulse width is 190 to 200uS. That way there will be no issues with any monitor brand.

              (I wonder if what went wrong here is that when the PT designers looked up the specs for V sync, they actually got the figure for the vertical blanking interval by mistake, which is around 800uS, closer to the value they chose)
              Last edited by Hugo Holden; April 27, 2019, 04:39 PM.

              Comment


                #8
                Also, PT used the same values (0.01uF and 100k) on their VDM1 video card.

                I think I know what went wrong here and how PT landed on the 600uS, this is one theory at least: Looking at a standard video signal from a video TV pattern/signal generator on a scope in a lab, due to the equalizing pulses on that signal (though not present on a signal from a computer graphics card), at a rough glance the "vertical block" appears to be about 9.5H periods long or 603uS.

                So probably, in the lab, when they were creating their video output signal for their VDM1 and the SOL-20 they chose that value in error (rather than looking up the specs for V sync), but of course got the H pulse width very close. And, it was fine probably on a lot of monitors and most people didn't notice an issue. Also, the cursor sits one of row of characters below the very top, so on TV's/monitors mostly the twist/timing errors were not too obvious on affected monitors.

                Comment


                  #9
                  Thanks for pointing this one out - it led me to find and fix two problems with my Sol-20 I didnít even know I had!

                  It also explains why a second 9 inch monitor I have - a Sony - tends to tear left on the top few raster lines more readily than the Panasonic monitor. Once I shortened the vertical sync width out of the Sol-20, both the Panasonic and the Sony monitors worked well. Before shortening the pulse, the Sony monitor had a more severe tear left than the Panasonic. That implies the vertical sync width on my Poly-88, with which the Sony monitor has a similar issue, probably has a long vertical sync pulse as well. Iíll be digging into that computer soon to see.

                  Mike

                  Comment


                    #10
                    Originally posted by deramp5113 View Post
                    Thanks for pointing this one out - it led me to find and fix two problems with my Sol-20 I didnít even know I had!

                    Mike
                    Its like that old saying, don't go looking for problems or you might find them !

                    I had a go at a formal calculation of what the time should be with this circuit. Its complicated by the fact that the capacitor probably doesn't have a non zero voltage at the start of the charge timing, as it has been discharging via the diode and one terminal probably sits close to 0.7V above the 5V rail, or it might be a tad lower than that. So when the cmos gate driving it goes low, to start the charging and timing event, the starting voltage on the capacitor is probably around +0.7v, before the charging begins. Then to calculate the output pulse time, an imaginary amount of time to get it to that 0.7V point has to be subtracted. In addition the gate threshold voltage of the 4049 is just an "estimate", its probably close to 2.5V though. See attached picture, it came out at 542uS with those assumptions.
                    Attached Files

                    Comment


                      #11
                      I pulled out my Poly-88 to see what it generates for vertical sync since I know my Sony monitor tears left at the top with my Poly-88 as well as my Sol-20.

                      I found the the Polymorphic VTI board generates a 500us vertical sync pulse. My Sony monitor tears left on the first few raster lines with this timing. My Panasonic monitor has the slightest tear just barely noticeable with the 500us vertical sync pulse. The VTI board generates the vertical sync pulse with counters and it is not easily shortened for further experiment. However, the experiments with the Sol-20 and a shortened vertical sync width allows me to conclude the following:

                      650us: Panasonic and Sony both exhibit problem
                      500us: Panasonic threshold, Sony exhibits problem
                      350us: Panasonic and Sony both work fine.

                      So both Polymorphic and Processor Technology made a design decision to go with much longer vertical sync widths than spec'd by RS-170. As you observed, the 500us-600us timing they both used is about the duration of the entire [pre-equalization, vertical sync, post-equalization] period, but if they saw that spec, they obviously saw the vertical sync width spec as well. Maybe some monitors of the day had a problem with the fact that neither board generates the H/2 equalization pulses and those monitors worked if the entire period was a vertical sync pulse instead?

                      Mike

                      Comment


                        #12
                        Originally posted by deramp5113 View Post
                        Maybe some monitors of the day had a problem with the fact that neither board generates the H/2 equalization pulses and those monitors worked if the entire period was a vertical sync pulse instead?

                        Mike
                        It is all very interesting. The equalization pulses are there in video signals to help with the exact interlace timing (the 1/2 line delay between fields) they are never present on non-interlaced signals from computers, early video games (at least that I have seen). Also I have never seen a sync separator in any monitor play up like this with a normal width vertical sync pulse. So its hard to know why they wanted a longer V sync when all the monitors of the time, were likely expecting a standard pulse, with or without equalization pulses.

                        Comment


                          #13
                          Mike,

                          One non-interlaced video signal I am very familiar with is the one from Atari's Pong Game in 1972.I have studied this circuit extensively and would have tried many different monitors on it over the years, never seen a problem after V sync in the stability of the H scan oscillator. This game was also designed to feed a television set (placed in their arcade cabinet), modified with an added video input, so it would act as a monitor. They chose 254uS as the vertical pulse width. That was convenient with the digital dividers they had there.

                          The signal from my IBM5155 shown in the original post is actually coming from an EGA card running in GCA mode. But clearly by then the computer industry had conformed to the standard for the V sync width. I have not actually tested the original IBM CGA card composite video output yet though.

                          The reason the lines tear at the top with the longer V. sync, is if the H pulses are not resolved by the sync separator right through the vertical interval where the V sync is and they drop out for some lines after the V.sync, it puts a glitch in the control(feedback voltage) in the horizontal AFC circuit. This causes a timing skew of the video and the tearing effect at the top after the sync. It can be masked to some extent by altering the filter components in the H AFC's loop. But really, everything works fine if the correct V sync is sent to the monitor. The way most sync separators work, the long vertical pulse upsets the bias at the base-emitter junction of the separator transistor with the common values used there.

                          Back in the early 1980's there was a quest on in video/Television work to find the best sync separator that was immune to high white in the picture content etc. Some used DC stabilization of the video followed by comparators with slice levels to pick off the sync. Others used logic circuits to regenerate the H pulses so that there is not disturbance at all from the vertical sync. I remember a clever two or three transistor circuit used in the sync separator for the control unit for the JVC KY2000 camera (I think it was the KM2000). It seemed impervious to any poor quality or abnormal video and always produced excellent separated syncs. But in TV's and Monitors, sometimes the sync separators were not that good.

                          Maybe it just took the computer industry a while to realize the standards for the V sync were important.

                          Comment


                            #14
                            Ok. You guys now got me interested in checking my Sol-20 systems. With VCF east coming up, I won’t be able to check for a week or so.

                            also remember PT offered their own monitor, which was a modified TV. So maybe it had something to do with that.

                            We should also ask Lee F. I think he designed the VDM and Sol-20 video circuit.

                            Cheers,
                            Corey

                            Comment


                              #15
                              [QUOTE=Corey986;568012

                              We should also ask Lee F. I think he designed the VDM and Sol-20 video circuit.

                              Cheers,
                              Corey[/QUOTE]

                              It would be great if he could read the thread and remark on it, if anyone knows how to contact him.

                              Certainly it seems, if you look at the scope recording on the first post of the separated syncs in the IBM-5155's Zenith monitor, with the Sol-20 as the video source, anything much over the 3x 63.5uS or 190uS width vertical pulse starts to upset the sync separator, so that particular sync separator, in that particular video monitor, needs to have an in spec vertical sync and in that respect is probably fussier than most, unless the bias is altered on the separator transistor to make it more tolerant.

                              Comment

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