Twospruces
Veteran Member
I am working on validating some overclocking modes for the TRS-80 Model 100.
To date, I have just been letting the system run at predefined clock rates, with pretty large jumps. I can tell when it really dies, but it is harder to say what is a reliable overclock setting, because it is statistical.
In order to get a better handle on this, I've been thinking I should find a way to generate or synthesize a finely tunable clock, so I can very accurately change the frequency / bus cycle time.
Then if I had a good way to measure an "error", I could plot Error Rate vs Cycle time.
Looking at such a thin in log-linear, I could then extrapolate to a suitable low error rate.
Question:
What would be a good way to measure a bus error? Any thoughts?
Any other ideas on how to deduce "safe overclocking"?
thanks!
To date, I have just been letting the system run at predefined clock rates, with pretty large jumps. I can tell when it really dies, but it is harder to say what is a reliable overclock setting, because it is statistical.
In order to get a better handle on this, I've been thinking I should find a way to generate or synthesize a finely tunable clock, so I can very accurately change the frequency / bus cycle time.
Then if I had a good way to measure an "error", I could plot Error Rate vs Cycle time.
Looking at such a thin in log-linear, I could then extrapolate to a suitable low error rate.
Question:
What would be a good way to measure a bus error? Any thoughts?
Any other ideas on how to deduce "safe overclocking"?
thanks!