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XTIDE Universal BIOS v2.0.0 beta testing thread

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  • irix
    replied
    I have the Beta 3 2.0.0 running on my 486 (Ti 486, actually a Cyric DX266) as it's bios did not recognise my 8gb SSD. This SSD is a better option than a CF-card for me, but I'm unable to find a smaller SSD than 8GB.
    Anyway: it gets recognised by XT IDE Universal Bios 2.0.0 beta 3, it works great, but every now and then it either doesn't recognise the drive at all, or just doesn't want to read certain files.
    Power the pc down, remove the SSD and re-insert it into the IDE port and it will run again.
    Or sometimes it just says "no boot sector found". Pull it of, put it back, running great again.

    Could this be a bug in the software or is this a hardware problem? (maybe one of the connectors isn't 100%) Just to know what to do, try or test next.

    Leave a comment:


  • dJOS
    replied
    Originally posted by Trixter View Post
    The only ways to speed that up is to either get a faster processor, or intentionally craft special partitions that use low numbers of clusters. The slowness comes from how DOS calculates free space, not from anything the XTIDE or your media is doing.

    On the plus side, it's only slow the first time you do DIR -- all subsequent DIRs are fast.
    That's pretty much what I suspected, thanks for confirming it.

    Leave a comment:


  • Trixter
    replied
    The only ways to speed that up is to either get a faster processor, or intentionally craft special partitions that use low numbers of clusters. The slowness comes from how DOS calculates free space, not from anything the XTIDE or your media is doing.

    On the plus side, it's only slow the first time you do DIR -- all subsequent DIRs are fast.

    Leave a comment:


  • dJOS
    replied
    Hi All, I'm running r580 on my Lo-tech Compact Flash ISA board in my Tandy 1000 EX and in general it is great - one question tho, is there anyway to speed up the free space calculation DOS does after doing a directory listing?

    Leave a comment:


  • ibmapc
    replied
    Originally posted by Krille View Post
    ...Indeed, so we are back to square one. Could the reason be some obscure CPU bug? Is it possible to replace the CPU on the Hotshot?
    I don't know which type of chip is on it. I can't even remember if it's socketed. But I'll take the cover off later this weekend and have a look.
    BTW, What advantage do the newer revs have over r588? So far I've been satisfied with r588, although I think it's not as fast as my ADP50L, but I think it's more reliable. I've had a few occurrences of data corruption wit the ADP50L. In fact, one of my future projects is to replace the bios on the ADP50L with an XTIDE bios to see if I can see larger drives and improve reliability with it.

    Leave a comment:


  • Krille
    replied
    Originally posted by Trixter View Post
    I would recommend against NOPs because that's not going to work with any other situation, whereas something that clears the prefetch queue (JMP $+2) or gives the bus time to settle (OUT EEh, AL) are true delays and will work consistently.
    Normally I would agree but this fix would be only for this specific combination of hardware so it doesn't really matter if it depends on CPU speed. In any case, it's all academic now anyway.

    Originally posted by ibmapc View Post
    So, maybe this is not a cache problem after all.
    Indeed, so we are back to square one. Could the reason be some obscure CPU bug? Is it possible to replace the CPU on the Hotshot?

    Leave a comment:


  • ibmapc
    replied
    Originally posted by ibmapc View Post
    ... I'll try it later with upper memory cache disabled and the r591 XUB and report back.
    Setting the HotShot with all upper memory cache disabled made no difference. When using ANY version of XUB newer than r588, the DOM is not found at boot time. I even tried disabling all cache including the lower 640k. Still no go. So, maybe this is not a cache problem after all.

    Leave a comment:


  • Trixter
    replied
    Originally posted by Krille View Post
    Perhaps one or two NOPs strategically placed in the XTIDE_INSW macro will suffice but that's assuming the problem only affects reads. Ideas and suggestions are very welcome!
    I would recommend against NOPs because that's not going to work with any other situation, whereas something that clears the prefetch queue (JMP $+2) or gives the bus time to settle (OUT EEh, AL) are true delays and will work consistently.

    Leave a comment:


  • ibmapc
    replied
    Actually Switches on HotShot are set as follows:

    OFF OFF ON ON 0CC000-0EFFFFH

    I was mistaken when I specified

    CC000 to DFFFF

    P.S.

    I'm willing to experiment as much as you like. It may take me some time to get to sometimes. Real life gets in the way of hobbies every now and then.

    Leave a comment:


  • Krille
    replied
    Originally posted by ibmapc View Post
    The default setting does not cache upper memory because most XTs don't have upper memory, however, mine has UMB in the D000 to EFFF range do to the 1megXT mod. Therefore, if the HotShot is set to not cache this region, performance is reduced quite a bit. I've looked over the manual which agrees with the info you found at minuszerodegrees and it appears the region CC000 to DFFFF is currently cached. This should not affect the XT-IDE bios at C8000. I'll try it later with upper memory cache disabled and the r591 XUB and report back.
    So the switches are set like this then?
    Code:
    SW4  SW5  SW6  SW7  Cached Area
    -------------------------------
    OFF  ON   ON   OFF  0CC000-0DBFFFH
    Note that if switch 6 is OFF (in other words, not making proper contact) then the cached area becomes 0C8000-0D7000H which would affect the XUB. (Yes, I'm desperately clutching at straws here.)


    Originally posted by Trixter View Post
    How do you think you'll be addressing this? JMP $+2, read from a dummy port like EEh, etc.?
    It really depends on the root cause of this problem and how much time and effort ibmapc (Greg?) is willing to spend experimenting with this. I'd like to minimize the impact on performance as much as possible so any code changes that's only needed for compatibility with this accelerator will probably be under a new define (named "HOTSHOT" I imagine). Perhaps one or two NOPs strategically placed in the XTIDE_INSW macro will suffice but that's assuming the problem only affects reads. Ideas and suggestions are very welcome!

    Leave a comment:


  • ibmapc
    replied
    Originally posted by Krille View Post
    Yeah, I can't see any other reason. I guess the size reduction made the entire read loop fit entirely in the cache which makes it so fast that (additional) I/O wait states are needed. Also, I just found this on minuszerodegrees.net. Apparently, the default setting is to have all caching disabled. That should tell you something... It also mentions that the memory used by "the PC-XT fixed disk controller" cannot be cached but I'm guessing that applies to controllers using memory mapped I/O. Or is that a specific controller?
    The default setting does not cache upper memory because most XTs don't have upper memory, however, mine has UMB in the D000 to EFFF range do to the 1megXT mod. Therefore, if the HotShot is set to not cache this region, performance is reduced quite a bit. I've looked over the manual which agrees with the info you found at minuszerodegrees and it appears the region CC000 to DFFFF is currently cached. This should not affect the XT-IDE bios at C8000. I'll try it later with upper memory cache disabled and the r591 XUB and report back.


    Originally posted by Krille View Post
    BTW, do you know how large the cache is?
    I do not know the size. I'll look over the board and see if I can identify the cache chip(s).

    Leave a comment:


  • Trixter
    replied
    Originally posted by Krille View Post
    I guess the size reduction made the entire read loop fit entirely in the cache which makes it so fast that (additional) I/O wait states are needed.
    How do you think you'll be addressing this? JMP $+2, read from a dummy port like EEh, etc.?

    Leave a comment:


  • Krille
    replied
    Originally posted by ibmapc View Post
    Well, funny you should mention cache. The HotShot does indeed cache all of the 640k base memory and some of the upper memory when in turbo mode. But, I believe It is set to only cache the D000h-EFFFh region. XT-IDE bios resides at C800h on my system so I think that area is not cached. I will check later on to make sure. Could this be the cause of the problem with the later builds in turbo mode?
    Yeah, I can't see any other reason. I guess the size reduction made the entire read loop fit entirely in the cache which makes it so fast that (additional) I/O wait states are needed. Also, I just found this on minuszerodegrees.net. Apparently, the default setting is to have all caching disabled. That should tell you something... It also mentions that the memory used by "the PC-XT fixed disk controller" cannot be cached but I'm guessing that applies to controllers using memory mapped I/O. Or is that a specific controller?

    BTW, do you know how large the cache is?

    Leave a comment:


  • pearce_jj
    replied
    Its more anecdotal - the XTIDE MUX design is picky with spinning disks, there was a list of devices that worked (or not) somewhere in one of these threads. Many devices do indeed work just fine.

    Leave a comment:


  • glitch
    replied
    Originally posted by pearce_jj View Post
    For the lo-tech 8-bit board, I included some delay gates in the command logic and this seems to resolve all compatibility issues.

    I wrote about it here - although I'm slightly reluctant to set it out again as some of my work has been copied recently.
    Thanks to Alan's clear, concise description of the problem, it'll be fixed in the eventual XT-IDE rev 4 board. He discussed the issue with me at VCF East this year, and followed up with a few emails afterwards.

    FWIW, the N8VEM designs are only affected by the timing in the read-from-IDE direction, writing to IDE should be fine with the inherent delay in the decode logic so no delay chain is necessary there.

    Originally posted by pearce_jj View Post
    Yes Alan it absolutely violates the timing, which is why it doesn't work with many devices in my opinion.
    Phew, at least it's an opinion only! Seriously, do we have a list of things that actually care about the MUX race condition? I've had one Flash module that didn't work with the N8VEM based MUX design, and I'm pretty sure it was a flaky Flash module. I could see this being an issue with fast ATA133 devices, though I think the fastest thing I've ever used with any of them was ATA100, and didn't have an issue (120 GB WD IDE drive).

    Leave a comment:

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