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XTIDE Universal BIOS v2.0.0 beta testing thread

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    Originally posted by Holmes View Post
    That's a problem, because I can't boot into 6.22 from any machine with a 5.25 floppy. Hmmm.
    How about if I give you a link to an image that you can copy to your PC and extract it right from there onto a floppy?
    PM me if you're looking for 3" or 5" floppy disks. EMail For everything else, Take Another Step

    Comment


      Originally posted by Stone View Post
      How about if I give you a link to an image that you can copy to your PC and extract it right from there onto a floppy?
      Thanks, but I managed to do it by finding a minimal dos 6.22 image and dskimage.exe for dos, transferring them over to the 5150, and writing the image directly from the 5150.

      Finally! The only problem is that the 6.22 version of xcopy still does NOT have the /h flag. Now why did I think it did have it?

      Comment


        Originally posted by Holmes View Post
        Finally! The only problem is that the 6.22 version of xcopy still does NOT have the /h flag. Now why did I think it did have it?
        I dunno... I would have thought it did as well. But you are right -- it doesn't.

        Grab a copy of XXCOPY16 and use that. It's a third party program and is not DOS dependant.

        There's also a FreeDOS XCOPY that I've been using which has the /H switch.
        PM me if you're looking for 3" or 5" floppy disks. EMail For everything else, Take Another Step

        Comment


          Originally posted by Stone View Post
          I dunno... I would have thought it did as well. But you are right -- it doesn't.

          Grab a copy of XXCOPY16 and use that. It's a third party program and is not DOS dependant.

          There's also a FreeDOS XCOPY that I've been using which has the /H switch.
          XXCOPY16 does look comprehensive. Dizzying array of options. It does seem to have a switch set called /clone which seems to be a good option for exactly what I want to do.

          Freedos looks like I'd need to install it, so I think I'll try xxcopy16.

          Thanks!

          Comment


            Originally posted by Holmes View Post
            XXCOPY16 does look comprehensive. Dizzying array of options. It does seem to have a switch set called /clone which seems to be a good option for exactly what I want to do.

            Freedos looks like I'd need to install it, so I think I'll try xxcopy16.

            Thanks!
            XXCOPY16 also has the /H switch in addition to the /clone switch!

            The XCOPY I have from Freedos does not need to be installed.

            PM me if you're looking for 3" or 5" floppy disks. EMail For everything else, Take Another Step

            Comment


              Originally posted by Stone View Post
              XXCOPY16 also has the /H switch in addition to the /clone switch!

              The XCOPY I have from Freedos does not need to be installed.

              Thanks for the link! I'll keep that in my PC box of tools for the future.

              I used XXCOPY16, and it did what I needed, and seems to have worked.

              Thanks again for all your help.

              Comment


                ATA emulator problems

                Odd request. I'm testing my IDE emulator with a Glitchworks XT-IDEv3 and Universal BIOS 2.0.0beta3 on a 5150 PC w/ 64KB. After implementing a few commands I didn't expect to be issued, I'm not getting correct data in BIOS calls. However I can fall into ROM BASIC and perform manual inp/outs and see that READ_MULTIPLE commands are working, the correct statuses are being set, and I'm getting the correct data in the latch registers. So I'm stumped...

                The BIOS doesn't print any ID string - almost like it saw nothing for the ID sector. But it does detect master and slave presence as I turn them on/off in the emulator. And of course I get boot sector not found and it fails to boot drive c. But I can issue an ID command in BASIC and see a well formed ID sector just fine.

                Quick summary of what my emulator does:

                1) When the command register is written, all the error bits are cleared, the busy bit is set, and the DRQ bit is cleared. All data transfer FIFOs are also reset to empty.
                2) Once the back-end of the emulator services the command and it's arguments, it clears the BSY bit, ensures DSC is set, DRDY is set, all error bits are cleared.. but leaves DRQ off for now.
                3) Once enough data has built up in the transfer FIFO such that a 256 word transfer can be performed at any speed (guaranteed no underflow), DRQ is set until 256 words actually get transferred.

                This all pretty standard ATA spec stuff. My emulator does not support IRQ mode at the moment.

                This is a quickly thrown together test setup - hence the 64KB 5150. I don't have a workable boot disk which is why I'm relying on ROM BASIC for testing. I can try to throw something more substantial together if there are no quick suggestions here.

                Thanks,

                -Alan
                "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

                Comment


                  I believe I have a theory, but cannot test until tonight. I think the XT-IDEv3 is violating the ATA setup and hold times wrt the upper/lower byte latches. Because the latch enables are being shoved through so much combinatorial logic on the board -> '688 address comparitor for IOSEL, further qualification of A0=0, A1=0, A2=0, the '138 mux selection for control strobes, and the inverters to right the logic, etc... and the IDE_RD signal is just a '245 buffered ISA_RD, my emulator is dropping the data presentation on the IDE data lines before the XT-IDEv3 has a chance to latch it in - on the upper byte.

                  I'll try delaying the data presentation some high number of internal clocks past strobe de-assertion and see if that helps. If the theory holds true however, the XT-IDEv3 is pretty flawed and compatibility problems will only get worse with newer generation PATA parts. Good thing not many are made any longer!
                  "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

                  Comment


                    Finally fixed it. It was a combination of the above and what I consider a serious design flaw in XT-IDE.

                    1) I had to add an extended hold delay that would persist the 16-bit IDE data while keeping all the data buffers enabled a configurable amount of time after the read strobe was de-asserted by XT-IDE.

                    2) For some reason the original XT-IDE designer decided to decode the high/low extended byte latch at the same address as the IDE device's CS1 address 0. While there is no ATA register mapped there, I had initially mapped my emulator's console UART data register (Raspberry Pi backend) to that address. The high byte latch and the IDE device were both driving the IDE data lines. While I suspect most IDE devices may either float the data bus during CS1:0 accesses, some probably do not. And it's reasonable to think many wont.

                    I suspect one or both of thee problems are causing most of the drive compatibility problems with XT-IDE cards of any version. At least my 5150 is booting DOS 2.1 now! yay!
                    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

                    Comment


                      Originally posted by eeguru View Post
                      Odd request. I'm testing my IDE emulator with a Glitchworks XT-IDEv3 and Universal BIOS 2.0.0beta3 on a 5150 PC w/ 64KB. After implementing a few commands I didn't expect to be issued, I'm not getting correct data in BIOS calls. However I can fall into ROM BASIC and perform manual inp/outs and see that READ_MULTIPLE commands are working, the correct statuses are being set, and I'm getting the correct data in the latch registers. So I'm stumped...

                      The BIOS doesn't print any ID string - almost like it saw nothing for the ID sector. But it does detect master and slave presence as I turn them on/off in the emulator. And of course I get boot sector not found and it fails to boot drive c. But I can issue an ID command in BASIC and see a well formed ID sector just fine.
                      I recommend using the latest revision available from www.xtideuniversalbios.org/binaries for your testing.

                      Beta 3 will ignore drives that don't pass the ATA-ID validation check. This check is simply an attempt to avoid data corruption on the drive if there's a problem communicating with it (due to bad cabling, soldering etc). However, it was discovered that a lot of perfectly good Compact Flash cards would fail the check and later on two different Western Digital Caviar models were found to also be incompatible with the ATA-ID validation so it was completely disabled in revision 580. (The code is still in there though and it can be re-enabled by removing the NO_ATAID_VALIDATION define from the makefile before building.)

                      Originally posted by eeguru View Post
                      If the theory holds true however, the XT-IDEv3 is pretty flawed and compatibility problems will only get worse with newer generation PATA parts. Good thing not many are made any longer!
                      So is this a problem with the XT-IDE v3 only or has it been confirmed to be a problem with all three versions of the XT-IDE card? I've seen comments on here indicating a timing problem with the XT-IDE v3 card but nothing really conclusive.
                      Looking for a cache card for the "ICL ErgoPRO C4/66d V"

                      Comment


                        Yes Alan it absolutely violates the timing, which is why it doesn't work with many devices in my opinion. For the lo-tech 8-bit board, I included some delay gates in the command logic and this seems to resolve all compatibility issues.

                        I wrote about it here - although I'm slightly reluctant to set it out again as some of my work has been copied recently.
                        Last edited by pearce_jj; April 1, 2017, 11:29 AM.

                        Comment


                          To add, I'm very interested in your experiments with the RPi, as I had floated the idea of using a Zero to emulate the Tandy DAC over the on Tandy sound board thread recently, using of course base board programming. Unfortunately I lack the time and the talent to pull it off but I was hopeing it might stir some interest and someone might jump in

                          Comment


                            Originally posted by ibmapc View Post
                            I have r588 running on mine and it works great. However, any revision newer than r588 doesn't work on my machine unless I run in non-turbo mode(I have an AST HotShot 286 Accelerator in my 5155), so I believe there is a timing issue with the newest revs (or an incompatibility with the HotShot). I think I was able to get r591 working if I disable the "Chuck Mod".
                            I'm stumped.

                            I've been going over all the changes I did in r589 many many times but I can't find a single change that could explain this timing problem. The slight size reduction could have been the reason if this had been a cached system but it isn't, is it? So what could possibly be the reason? Every branch destination suddenly fell into perfect alignment? Shouldn't matter much since the code is still traveling over an 8-bit bus. Very little of the actual code changes should affect the operation of an XTIDE card;
                            • XTIDE_Universal_BIOS/Inc/RamVars.inc
                              This change makes the stack pointer WORD aligned which speeds up stack accesses significantly (on a 16-bit bus) and this could possibly be the reason if it wasn't for the fact that it only affects builds without MODULE_EBIOS which means that of the official builds, only the xt_tiny build is affected.
                            • XTIDE_Universal_BIOS/Src/Device/IDE/IdeCommand.asm
                              This change involves code used to reset the drives. I don't see how this could be the reason if the computer can boot successfully using the slow 8088 and then start to behave strangely when the acceleration is activated since there are no resets being done at that point.
                            • XTIDE_Universal_BIOS/Src/Device/IDE/IdePioBlock.asm and XTIDE_Universal_BIOS/Src/Device/IDE/IdeTransfer.asm
                              Here I moved some segment swapping code from IdePioBlock.asm to IdeTransfer.asm. This change only affects the write routines so this shouldn't (immediately) cause corrupted reads.
                            • XTIDE_Universal_BIOS/Src/Handlers/Int13h.asm
                              Here I expanded a couple of macros so I could optimize away a single instruction at the end of the interrupt handler. So this is not the reason since it's run after the transfers.
                            • XTIDE_Universal_BIOS/Src/Handlers/Int13h/Tools/Address.asm
                              Optmiized away a couple of instructions. This is insignificant and most importantly, not in the middle of some I/O operation so this is not it.


                            The rest of the changes are not relevant. They mostly affect boot menu code and some of the virtual serial drive code and controllers other than the XTIDE such as the VLB controllers.

                            So yeah, I'm stumped.
                            Looking for a cache card for the "ICL ErgoPRO C4/66d V"

                            Comment


                              Originally posted by Krille View Post
                              I'm stumped.

                              ...The slight size reduction could have been the reason if this had been a cached system but it isn't, is it? ...
                              Well, funny you should mention cache. The HotShot does indeed cache all of the 640k base memory and some of the upper memory when in turbo mode. But, I believe It is set to only cache the D000h-EFFFh region. XT-IDE bios resides at C800h on my system so I think that area is not cached. I will check later on to make sure. Could this be the cause of the problem with the later builds in turbo mode?

                              Comment


                                Originally posted by pearce_jj View Post
                                For the lo-tech 8-bit board, I included some delay gates in the command logic and this seems to resolve all compatibility issues.

                                I wrote about it here - although I'm slightly reluctant to set it out again as some of my work has been copied recently.
                                Thanks to Alan's clear, concise description of the problem, it'll be fixed in the eventual XT-IDE rev 4 board. He discussed the issue with me at VCF East this year, and followed up with a few emails afterwards.

                                FWIW, the N8VEM designs are only affected by the timing in the read-from-IDE direction, writing to IDE should be fine with the inherent delay in the decode logic so no delay chain is necessary there.

                                Originally posted by pearce_jj View Post
                                Yes Alan it absolutely violates the timing, which is why it doesn't work with many devices in my opinion.
                                Phew, at least it's an opinion only! Seriously, do we have a list of things that actually care about the MUX race condition? I've had one Flash module that didn't work with the N8VEM based MUX design, and I'm pretty sure it was a flaky Flash module. I could see this being an issue with fast ATA133 devices, though I think the fastest thing I've ever used with any of them was ATA100, and didn't have an issue (120 GB WD IDE drive).
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