• Please review our updated Terms and Rules here

QuikLoader board

D

Dwight Elvey

Veteran Member
Joined
Jun 21, 2003
Messages
4,995
Location
Santa Cruz
Hi
I'm still hoping to find a manual for this board.
It is cool. It allows on to put most anything
that can be loaded from disk onto EPROMs
and then transfered to RAM from the card.
So far, I've been able to use it with what is on
it but I'd like to do some of my own code for
it. With out instructions, it'll be tough.
Cool thing is it has both DOS3.3 and ProDOS
in the EPROMs.
Dwight
 
Dwight Elvey said:
Hi
I'm still hoping to find a manual for this board.
It is cool. It allows on to put most anything
that can be loaded from disk onto EPROMs
and then transfered to RAM from the card.
So far, I've been able to use it with what is on
it but I'd like to do some of my own code for
it. With out instructions, it'll be tough.
Cool thing is it has both DOS3.3 and ProDOS
in the EPROMs.
Dwight
Click to expand...

Hi
I just thought I'd pass on that I finally found some Docs
for the SCRG QuikLoader board.
A fellow in France had mauals and all on disk, including the
disk images to do things like building new ROM images.
For anyone wanting copies, he posted it all to the Asimov
collections under the ROM directory.
I've not done anything yet with it but plan to soon.
For those that are not familiar with it , it takes binary and
BASIC programs that would normally be on disk and allows one
to load then into RAM with quick key strokes. I've found it
really handy as I've been doing analysis of programs that
often require reloading DOS after things go wild.
It is not the Apple ROM card you usually see on eBay and
it is definitely something all would want.
It would conflict with any card that takes over the boot process
early on, such as the IA SwyftCard ( something else I'm playing
with ).
Dwight
 
Wow, that IS pretty darn cool. Will it work on a GS? Could you put larger capacity ROMs in it and load GS/OS from ROM?
 
Hi
Not sure if it works in a GS but I suspect it could be made to work. It can
hold up to 6 ea 27512 chips and can load multiple chips at a time.
That is 64K bytes times 6 minus some overhead.
It takes less than 2 seconds to load DOS 3.3 and BASIC.
Dwight
 
I just bought one off of Epay. Mine has EEPROMS installed. I am not sure yet if you can program them while installed in the card. I have all of the software if you need it. Mine is loaded with DOS, and a bunch of games an utilities.

Jeff
 
The Quikloader card alone can't program the EPROMs/EEPROMs. You need a separate programmer to make your own ROMs.
 
I discuss the SCRG QuikLoader in great detail in my DOS 4.1 document found on my website www.applecored.net. I made a simple hardware change using an unused gate in order for the board to respond to slot addresses. And I developed a far superior operating system I call EOS, or EPROM Operating System. An EPROM burner is required to program the EPROMs, such as the SCRG PromGramer. The last generation board can support up to 8 27512 EPROMs. Seriously, I only use 3 27512s on my board for all the tools I need. I believe my EOS loads DOS 4.1 way faster than 3 seconds.
 
I have two PDF's that are similar to the manuals I own for the quikLoader. I would be happy to email these PDFs to any interested party.
 
wpvrbancic said:
I discuss the SCRG QuikLoader in great detail in my DOS 4.1 document found on my website www.applecored.net. I made a simple hardware change using an unused gate in order for the board to respond to slot addresses. And I developed a far superior operating system I call EOS, or EPROM Operating System. An EPROM burner is required to program the EPROMs, such as the SCRG PromGramer. The last generation board can support up to 8 27512 EPROMs. Seriously, I only use 3 27512s on my board for all the tools I need. I believe my EOS loads DOS 4.1 way faster than 3 seconds.
Click to expand...

I'm currently doing a reboot of the quikloader cards. I'm having issues with getting the flash rom to behave correctly to allow writing to it but the prototypes work happily with the flash programmed externally.

The QLOS is buggy with 27512 images so I'd be keen to see your OS in action.

quikloader.jpg
 
These things can be tricky with timing. I use a 28C64 that I used on my 6530 adapter. I wrote the data into it on the KIM-1, in place. Looking at the specs, I found that the 6502 was too slow to do block writes. I did it using 'a byte at a time' mode, rather than the block mode. This worked fine.
Dwight
 
At the moment the flash is not going into command mode so we cant even get a chip ID from it. So something about the write cycle timing it doesnt like.
 
What method are you using, the WR or the CE timing. What signals are you using to qualify these signals? Also, you may have to look at the JEDEC file and the fuse map to determine if the control signals have no glitch possibilities. Making logic match and making a glitch free write strobe are two different things. Sometimes using a GAL or PAL requires an external inverter on the qualifying signal or external gate to make a glitch free output. Clocks are not the same as logic signals. You what the qualifying signal to end up on the last gate of the logic sequence and not earlier in the logic path.
Looking at the Microchip timing, they don't show any different addresses between the addresses. I wonder if you might need to hold the last address and data between WR or CE pulses. On a programmer it sequences address and data as the diagram shows while in circuit, there is active code between the elements of the unlocking. I can't imagine that they expect it to be like that but the timing diagram doesn't show a typical X time between the elements of the timing sequence. It is more likely something in the qualifying of the write.
Dwight
 
The qualifying signal ( usually the phase 2 clock as I recall on the 6502 ) has to end up as the last gate in the logic path. This can be a problem for circuits that are not designed specifically for clocking. The logic assembler you have may not understand the usage of the signals and create incorrect logic order. When I did my PAL, I manually wrote the JEDEC file to ensure it didn't optimize the order of the gating and mess up the timing.
Dwight
 
Last edited:
On the Saturn Reboot I combine the WR signal with Q3 effectively delaying WR being asserted until midway through the CPU phase and that solved timing issues on some clones that had issues. The same technique should work for the QL cards. So far I've tried WR timing but not CE. At one stage was able to read the ID from a Macronix flash but not the SST but because the MX chip is no longer in production I kept tinkering to try to get the SST chip to work. The current GAL timing wont work with either chip, so I need to recreate the earlier GAL coding. I now have an MX chip in a different package (PLCC) that is still in production that I hope will work with the earlier GAL timing.

I probably should setup the logic analyser on it but I've been lazy.
 
You must log in or register to reply here.
Back
Top